Distributed Shared Memory Architecture for Scalable SMP Systems

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Solution Overview

Problem

Current supercomputer architectures face challenges with scalability and cost due to proprietary components and inefficiencies in shared memory systems, limiting the deployment of shared memory supercomputers and restricting the number of software codes that can be run.

Innovation Solution

A scalable symmetric multiprocessing (SMP) supercomputer system is implemented using a tightly coupled cluster of homogeneous multi-core servers with high-speed network connections supporting remote direct memory access (RDMA), employing a transactional distributed shared memory model with local and global memory partitions, and distributed thread and mutex management to maintain memory consistency and optimize disk I/O operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If hardware cache coherent architecture is used, then memory access coordination is simplified, but scalability is limited to about 500 processors

Engineering Contradiction:

Improvememory access coordinationVSAvoidscalability

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The system segments memory management into page-level units rather than cache-line units, allowing independent management of larger memory blocks. This segmentation enables scalable architecture by reducing the overhead of coordination as processor count increases, directly resolving the scalability limitation of hardware cache coherent systems.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a page table and operating system-mediated memory management as an intermediary layer between processors and physical memory. This software-based mediation replaces hardware-based cache coherence protocols, enabling scalable shared memory access without the 500-processor limitation while maintaining coordination simplicity through virtual memory abstraction.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If shared virtual memory with demand paging is implemented, then scalability is improved, but performance deteriorates due to software overhead

Engineering Contradiction:

ImprovescalabilityVSAvoidperformance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by pre-allocating and pre-fetching memory pages into local memory before they are needed for execution. This reduces demand paging overhead by having memory pages ready in advance, improving performance while maintaining the scalability benefits of virtual memory architecture.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous memory management by maintaining page tables and memory mappings in active state, allowing seamless access to shared memory pages across processors. This continuity eliminates repeated software overhead for memory management operations, improving performance while preserving scalability.

Inventive Principle:

Principle #20Continuity of useful action

3Adaptability or versatility

If proprietary components are used, then shared memory architecture is achieved, but cost increases significantly

Engineering Contradiction:

Improveshared memory capabilityVSAvoidcost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent implements a universal shared memory architecture that works across standard commodity hardware platforms. By using software-based virtual memory and page tables instead of proprietary hardware components, the system achieves shared memory capability on off-the-shelf processors and memory systems, dramatically reducing cost while maintaining functionality.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system replaces expensive proprietary shared memory hardware with software-based virtual memory pages that can be dynamically allocated and freed. This approach uses inexpensive standard memory components managed through software, achieving the same functional result at fraction of the cost of proprietary hardware solutions.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS8607004B2Distributed symmetric multiprocessing computing architecture

Publication Date: 2013.12.10 ANDERSON RICHARD S

AI summary

Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous multi-core servers. The level of processor and memory performance achieved is suitable for running applications that currently require cache coherent shared memory mainframes and supercomputers. The architecture combines new operating system extensions with a high-speed network that supports remote direct memory access to achieve an effective global distributed shared memory. A distributed thread model allows a process running in a head node to fork threads in other (worker) nodes that run in the same global address space. Thread synchronization is supported by a distributed mutex implementation. A transactional memory model allows a multi-threaded program to maintain global memory page consistency across the distributed architecture. A distributed file access implementation supports non-contentious file I/O for threads. These and other functions provide a symmetric multiprocessing programming model consistent with standards such as Portable Operating System Interface for Unix (POSIX).