Distributed SSD Architecture with Flash Processor Units
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Solution Overview
Problem
Conventional solid-state drive (SSD) flash controllers provide slow read and write times due to the concentration of wear-leveling, error correction, and bad block management operations, which limits the performance and reliability of SSDs.
Innovation Solution
A distributed architecture featuring a serial data bus, multiple flash processor units (FPUs), and a supervisor processing unit, where each FPU manages a group of flash units and the supervisor unit coordinates data transfer, enabling efficient data access and reducing the workload on the supervisor CPU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single flash controller is used to manage wear-leveling, error correction, and bad block management operations, then device complexity is reduced, but read and write times become slow
Solution Approach 1:
The patent divides the single flash controller into multiple distributed flash processor units (FPUs), each capable of independently managing wear-leveling, error correction, and bad block management operations for specific flash memory groups. This segmentation enables parallel processing of multiple operations simultaneously, significantly improving read and write speeds while distributing the computational workload across multiple specialized units.
2Quantity of substance
If MLC flash memory is used to increase storage capacity and reduce cost, then storage density is improved, but bit error rate increases reducing reliability
Solution Approach 1:
The patent implements enhanced feedback mechanisms through the distributed FPUs that continuously monitor and correct errors in MLC flash memory. Each FPU performs real-time error correction coding (ECC) and wear-leveling operations, adjusting write distributions and correcting bit errors dynamically. This feedback system maintains high reliability despite the inherently higher error rates of MLC technology by continuously detecting and correcting errors before they affect data integrity.
3Duration of action of stationary object
If wear-leveling operations are performed to prolong flash memory life, then duration of action is improved, but processing time is consumed
Solution Approach 1:
The patent implements continuous wear-leveling operations through the distributed FPU architecture, where wear-leveling is performed continuously in the background during normal read and write operations rather than as periodic batch processes. Each FPU continuously monitors flash unit usage patterns and dynamically redistributes write operations to balance wear across all flash units, extending flash memory life without introducing noticeable delays to data access performance.
Data Source
AI summary
In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.