Distributed Storage Agents for In-Memory Data Transfer Bottlenecks

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Solution Overview

Problem

Existing processing systems, such as CPUs and GPUs, suffer from bottlenecks due to shared memory architectures, leading to inefficiencies in data transfer and processing speeds, particularly in applications like data analytics where network bandwidth and memory size limitations hinder scalability.

Innovation Solution

Implementing memory processing modules (MPMs) that integrate processing elements directly on the same semiconductor die as memory banks, reducing the need for shared buses and enabling parallel processing within memory appliances like XDIMMs and IMPUs, which allow for localized data processing and reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If shared memory architecture is used in CPUs and GPUs, then memory capacity is improved, but processing speed and data transfer efficiency deteriorate due to bottlenecks

Engineering Contradiction:
Improvememory capacityVSAvoidprocessing speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides the monolithic shared memory architecture into distributed memory banks, each with its own local processing units. This segmentation eliminates the single bottleneck by creating multiple independent data paths, allowing parallel access without contention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a centralized shared memory model to a distributed memory architecture where processing units are embedded within memory banks themselves. This dimensional reorganization creates a many-to-many connectivity pattern instead of a star topology, fundamentally changing the data access paradigm.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If data is transferred over network in data analytics applications, then data accessibility is improved, but network bandwidth limitations cause bottlenecks

Engineering Contradiction:
Improvedata accessibilityVSAvoidnetwork bandwidth
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent extracts the processing function from centralized CPUs/GPUs and places it directly within the memory appliance. This eliminates the need for continuous data transfer over the network, as data can be processed in-place within the memory bank where it resides.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces memory appliances with embedded processing units as intermediaries between storage and compute resources. These intermediaries perform data preprocessing, filtering, and computation locally, reducing the volume of data that needs to traverse the network to external processors.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If shared buses are used for memory access, then system simplicity is maintained, but data transfer efficiency and parallel processing capability deteriorate

Engineering Contradiction:
Improvesystem simplicityVSAvoidparallel processing capability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent merges the processing units directly into the memory bank structure, creating integrated memory-compute modules. This consolidation eliminates the need for separate shared buses, as data can be processed in-place without requiring transport over external interconnects.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent enables memory banks to perform processing operations independently without requiring external control for each operation. The embedded processing units can execute instructions autonomously on data residing in their local memory, reducing dependency on centralized control and external communication.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12487915B2Read performance from disaggregated storage using distributed storage agents
Publication Date: 2025.12.02 NEUROBLADE LTD
  • US12487915B2 patent drawing
  • US12487915B2 patent drawing
  • US12487915B2 patent drawing

AI summary

A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.