Distributed Syncbox for Hardware Accelerator Synchronization

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Solution Overview

Problem

In video processing systems, centralized synchronization of hardware accelerators leads to unpredictable synchronization times due to processor interrupt latency and priority dependencies, which can become a bottleneck as image resolutions increase and processing complexity grows, burdening the CPU and affecting size and power usage.

Innovation Solution

A distributed synchronization scheme using a synchronization module, referred to as the 'syncbox,' is implemented, where each hardware accelerator has a dedicated syncbox that receives activation events, schedules tasks, and signals completion, connected through an OCP network, allowing for message-passing and programmability to manage activation and acknowledgement messages independently of the CPU.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If centralized CPU control is used for hardware accelerator synchronization, then system coordination is achieved, but synchronization time becomes unpredictable and CPU burden increases

Engineering Contradiction:
Improvesynchronization coordinationVSAvoidsynchronization time variability
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The centralized CPU synchronization function is segmented and distributed to individual syncbox modules attached to each hardware accelerator. Each syncbox independently manages synchronization for its associated accelerator, eliminating the bottleneck of centralized CPU control and reducing synchronization time variability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Syncbox modules serve as intermediary components between hardware accelerators and the CPU. These intermediaries handle synchronization tasks locally, reducing direct CPU involvement and eliminating interrupt latency issues while maintaining reliable system-wide coordination through standardized message passing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If more hardware accelerators are added to handle higher resolutions, then processing capability increases, but CPU scheduling burden increases

Engineering Contradiction:
Improvevideo processing capabilityVSAvoidCPU scheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments synchronization responsibilities by assigning dedicated syncbox modules to each hardware accelerator. This segmentation allows each accelerator to be managed independently, enabling the addition of more accelerators for higher resolution processing without proportionally increasing CPU scheduling complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each hardware accelerator with its attached syncbox module becomes self-sufficient for synchronization tasks. The syncbox autonomously manages activation events and task scheduling for its associated accelerator, reducing the CPU's scheduling burden while allowing the system to scale to handle higher resolutions.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If explicit priority schemes are implemented for interrupt lines, then task scheduling control improves, but synchronization time becomes harder to predict

Engineering Contradiction:
Improvetask scheduling controlVSAvoidsynchronization time predictability
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The syncbox module acts as an intermediary that decouples priority-based scheduling from interrupt latency issues. By handling task activation and synchronization locally without relying on CPU interrupt priorities, the system maintains ease of task scheduling control while achieving predictable synchronization times independent of interrupt line configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8463865B2Video synchronization with distributed modules
Publication Date: 2013.06.11 TEXAS INSTRUMENTS INC
  • US8463865B2 patent drawing
  • US8463865B2 patent drawing
  • US8463865B2 patent drawing

AI summary

A digital system is provided that includes a number of hardware accelerators. Each hardware accelerator is paired with a synchronization module that is configured to determine when a scheduled task can be started. Each synchronization module includes a network interface configured to send and receive messages to and from other synchronization modules and a configuration interface configured to receive task information from a host processor. Each synchronization module also includes a task scheduler configured to select a task in response to a received message and a task processor interface configured to initiate the selected task on a hardware accelerator coupled to the synchronization module.