Distributed Table-Driven Power Mode Computation for SoC
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Solution Overview
Problem
Global power management controllers face inefficiencies in managing clock and voltage states due to the need for extensive data querying and complex trade-offs in disabling power resources, particularly when dealing with embedded Vdd switches, which complicates power mode transitions and affects battery life in portable devices.
Innovation Solution
A distributed table-driven approach for managing clocks, Vdd, and embedded Vdd switches, where hardware blocks are organized in a tree-like hierarchy with transition tables that allow for efficient computation of optimal power modes by considering benefit and latency, enabling selective disabling and enabling of power resources based on expected idle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global power management controller queries extensive data about SoC state to decide power modes, then power mode decisions can be made, but the complexity and time required for decision-making increases
Solution Approach 1:
The patent divides the SoC into multiple hierarchical levels (top-level controller, domain controllers, and individual hardware blocks). Each level manages its own power resources and makes local decisions, eliminating the need for a single global controller to query all SoC data. This segmentation reduces controller complexity while maintaining reliable power management through distributed decision-making.
2Loss of energy
If Vdd is disabled when reference count reaches zero, then power consumption is reduced, but state loss occurs requiring time-consuming state saving
Solution Approach 1:
The patent implements state saving as a preliminary action before disabling Vdd. When the reference count reaches zero, the system automatically saves the hardware block state to retention memory before cutting power. This ensures that power can be reduced immediately while preserving all necessary state information for future restoration, eliminating the trade-off between power savings and state preservation time.
Solution Approach 2:
The patent introduces retention memory as an intermediary between the hardware block and power supply. This intermediary storage mechanism allows state to be preserved during the transition from powered-on to powered-off state, enabling Vdd to be disabled for power savings while the intermediary retains all block state information for later restoration.
3Loss of energy
If clocks are disabled for power management, then power consumption is reduced, but the transition takes only a few cycles compared to Vdd disabling
Solution Approach 1:
The patent implements dynamic power management where the system automatically selects between clock disabling and Vdd disabling based on current conditions. The controller monitors reference counts, idle times, and state complexity to dynamically choose the most appropriate power management action. This dynamic approach optimizes power savings while adapting to varying system states and requirements.
4Adaptability or versatility
If embedded Vdd switches are used in hardware blocks, then power control flexibility is improved, but the trade-off in cycles and complexity increases
Solution Approach 1:
The patent enables hardware blocks with embedded Vdd switches to manage their own power states autonomously. Each block monitors its own reference count and can independently open or close its Vdd switch based on local conditions. This self-service capability provides fine-grained power control flexibility while distributing the management complexity to individual blocks rather than centralizing it in a controller.
Data Source
AI summary
A method for computing the optimal power mode for a system-on-chip (SoC) in which both the clock and Vdd settings are controlled. Information from hardware blocks is synthesized into a global power mode for the entire SoC. The clocks can be disabled or enabled, and Vdd voltages can be disabled, set at a nominal operating level, and set at a retention level in which the state of memory and registers is retained.