Distributed Tag Directory for Multi-Core Cache Coherency
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Solution Overview
Problem
As the number of core memory groups in multi-core processors increases, the burden on the directory cache and pipeline circuit in the home agent grows, leading to inefficiencies in cache coherency management and memory access control.
Innovation Solution
Implementing a tag directory within each core memory group to store data possession information of other core memory groups, reducing the need for a home agent and allowing the cache control circuit to directly check the tag directory for cache hits, thereby reducing circuit scale and processing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of core memory groups increases to improve processing power, then the circuit scale of the directory cache and the number of processes in the home agent pipeline increase, leading to increased device complexity and processing time
Solution Approach 1:
The patent segments the directory cache functionality by creating separate directory caches in each core memory group rather than using a centralized directory cache. Each directory cache stores possession information only for its own core memory group, dividing the overall directory cache into multiple smaller, independent segments that can operate autonomously.
Solution Approach 2:
The patent introduces a new dimensional approach by adding a cross-bar switch network that enables direct peer-to-peer communication between core memory groups. This adds a new communication dimension that bypasses the traditional home agent pipeline, allowing data requests to be routed directly between CMGs without passing through centralized control structures.
2Power
If the number of core memory groups increases to improve processing power, then the number of processes in the home agent pipeline increases, leading to increased processing time
Solution Approach 1:
The patent extracts the directory cache functionality from the home agent structure and places it directly within each core memory group. This removal of the directory cache from the home agent's processing pipeline eliminates the need for home agents to sequentially process directory cache lookups, thereby reducing the number of processes in the pipeline and decreasing processing time.
Solution Approach 2:
The patent implements a direct data request mechanism that allows core memory groups to skip the traditional home agent mediation step. When a cache miss occurs, the requesting CMG can directly issue data requests to other CMGs using the cross-bar switch network, rushing through the data acquisition process without waiting for home agent pipeline processing.
3Reliability
If a centralized directory cache is used in the home agent to track data possession information, then cache coherency can be maintained, but the circuit scale and processing complexity increase with more core memory groups
Solution Approach 1:
The patent segments the centralized directory cache into distributed directory caches, with each CMG maintaining its own directory cache for tracking possession information of data blocks managed by its CMG. This segmentation maintains cache coherency through decentralized tracking while reducing the complexity burden on any single home agent structure.
Solution Approach 2:
Each core memory group serves itself by maintaining its own directory cache and directly managing data possession information for its managed memory blocks. This self-service approach eliminates the need for complex centralized home agent structures to track and manage coherency information for all CMGs, thereby reducing overall system complexity while maintaining reliability.
Data Source
AI summary
An arithmetic processing apparatus includes, a plurality of core memory groups, each of core memory groups including a plurality of arithmetic processing circuits, cache memory circuitry, shared by the plurality of arithmetic processing circuits, including a cache memory, a cache tag that stores a state of the cache memory, a tag directory that stores data possession information by a cache memory in another core memory group, and a memory access control circuit that receives a first memory access request from the cache memory circuitry and controls access to a memory other than a cache memory included in the cache memory circuitry, and a cache memory control circuit that receives a second memory access request from the arithmetic processing circuits and a third memory access request from the another core memory group and controls access to the cache memory.