Distributed Test Site Processors for Memory Redundancy Analysis

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Solution Overview

Problem

Conventional automated test equipment (ATE) systems for memory devices face latency issues during redundancy analysis (RA) due to the need for dedicated processors, which increases costs and complexity without significantly improving test throughput.

Innovation Solution

Implementing a distributed processing system with multiple test site processors (TSPs) that analyze redundancy data in parallel, allowing the main test controller to focus on other tasks and eliminating the need for additional processor hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a dedicated processor is added to compute redundancy analysis, then test throughput is improved, but device complexity and cost increase

Engineering Contradiction:

Improvetest throughputVSAvoidprocessor hardware complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent makes existing test site processors multi-functional by enabling them to perform both their original testing functions and redundancy analysis computations. Each TSP is configured to control testing routines for multiple DUTs and simultaneously analyze redundancy data from those same or other DUTs, eliminating the need for dedicated RA processors while improving throughput through parallel processing

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Device complexity

If redundancy analysis is performed within the main test program, then device complexity is reduced, but test latency increases

Engineering Contradiction:

Improveprocessor hardware complexityVSAvoidtest latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent segments the testing system into multiple independent test site processors, each capable of autonomously performing both testing and redundancy analysis. This segmentation allows parallel execution of RA operations across multiple TSPs simultaneously, rather than having a single main test program sequentially process each DUT, thereby reducing overall test latency while maintaining software-based implementation

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent enables continuous parallel processing by having multiple TSPs simultaneously control testing routines and analyze redundancy data for different DUTs. While one TSP is performing RA on a first DUT, other TSPs are concurrently performing RA on additional DUTs, eliminating idle time and maintaining continuous productive action across the entire test system

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS9330792B2Testing memory devices with distributed processing operations

Publication Date: 2016.05.03 ADVANTEST CORP

AI summary

Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.