Distributed Time Sync in DAG Networks Using Timing Error Correlation

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Solution Overview

Problem

Large-scale low power and lossy networks (LLNs) face difficulties in maintaining synchronization among wireless resource-constrained devices, leading to potential loss of synchronization and prolonged resynchronization times due to long sleep intervals and cumulative timing errors, which can result in unreliable communications and reduced network robustness.

Innovation Solution

A method for distributed time synchronization in a directed acyclic graph (DAG) network, where constrained wireless network devices receive timing error messages from neighboring available parent devices and correlate these errors to synchronize their local clocks with a master clock, using a statistical mean to align with the most probable position of the master clock, thereby reducing cumulative drift and improving synchronization across the network.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If LLN devices use long sleep intervals to conserve energy, then energy consumption is reduced, but synchronization reliability deteriorates and resynchronization time increases

Engineering Contradiction:
Improveenergy consumptionVSAvoidsynchronization reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The system performs preliminary actions by having parent devices send timing error messages before child devices need to resynchronize. This allows child devices to accumulate timing error data during their sleep intervals and perform rapid correlation-based synchronization when awake, maintaining reliability while conserving energy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces timing error messages as an intermediary mechanism. Instead of direct synchronization between sleeping child devices and the master clock, parent devices act as intermediaries by collecting and propagating timing error information, enabling indirect but reliable synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If LLN devices perform randomized search during reboot to resynchronize, then eventual resynchronization is achieved, but resynchronization time extends to days or weeks

Engineering Contradiction:
Improveresynchronization capabilityVSAvoidresynchronization time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements feedback by having parent devices send timing error messages that contain information about the master clock's timing. Child devices use this feedback to directly calculate their synchronization offset without random searching, reducing resynchronization time from weeks to immediate or near-immediate recovery.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Parent devices perform preliminary actions by continuously collecting and propagating timing error information from the master clock. When a child device needs to resynchronize, this preliminary information is already available, eliminating the need for lengthy randomized search procedures.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If LLN devices correlate timing errors from multiple parent devices, then synchronization accuracy improves, but device complexity increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidsynchronization algorithm complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation by using timing error offsets rather than absolute timing values. This simplification allows child devices to correlate multiple parent device timing errors using basic statistical operations (mean calculation), achieving high synchronization accuracy without complex algorithms.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system uses copying by having child devices receive and process copies of timing error information from multiple parent devices. Instead of directly measuring and comparing complex timing parameters, devices work with simplified copied error offset values, reducing computational complexity while maintaining precision.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11751156B2Distributed time sync in a directed acyclic graph of a time-synchronized network based on correlating timing information from higher network devices
Publication Date: 2023.09.05 CISCO TECHNOLOGY INC
  • US11751156B2 patent drawing
  • US11751156B2 patent drawing
  • US11751156B2 patent drawing

AI summary

In one embodiment, a method comprises: receiving, by a constrained wireless network device comprising a local clock, a plurality of messages from respective neighboring wireless network devices advertising as available parent devices in a directed acyclic graph of a time-synchronized network that is synchronized to a master clock device; determining, by the constrained wireless network device, a corresponding timing error of the local clock relative to each message output by the corresponding available parent device; and executing, by the constrained wireless network device, a distributed time synchronization of the local clock with the master clock device based on correlating the respective timing errors relative to the local clock.