Distributed Timer Synchronization Across ARM Devices
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Solution Overview
Problem
Current systems with multiple processing elements on a single device or across multiple devices face challenges in synchronizing a global timer value, leading to delays and inefficiencies, especially when a large number of processing elements are involved.
Innovation Solution
The system achieves initial and ongoing synchronization by determining and minimizing the offset between timers across multiple ARM devices linked in a coherent memory fabric, either by adjusting the rate at which timers are incremented or by writing the timer value from a master device to slave devices, ensuring all devices maintain a consistent timer value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated parallel buses are used to send global timer values to each processing element, then each processing element can access the timer value, but the system becomes complex and inefficient when a large number of processing elements are present
Solution Approach 1:
The patent merges the timer distribution function into a shared resource model where multiple processing elements across different devices access a common timer value through the interconnect fabric, eliminating the need for separate dedicated buses to each processing element. This consolidation reduces overall system complexity while maintaining timer accessibility.
Solution Approach 2:
The interconnect fabric serves multiple functions simultaneously: it provides memory access, I/O communication, and timer value distribution across all devices and processing elements. This multi-functional approach eliminates the need for specialized dedicated timer buses, reducing device complexity while ensuring reliable timer synchronization.
2Adaptability or versatility
If multiple devices are linked together to form a coherent memory fabric, then processing elements can access resources across devices, but synchronizing the global timer across all devices becomes more difficult
Solution Approach 1:
The system implements feedback mechanisms where timer values are periodically distributed and synchronized across all devices in the coherent memory fabric. Each device can detect timer offsets and adjust accordingly, ensuring consistent timer values are maintained across the distributed system despite the complexity of multi-device architecture.
3Reliability
If a global timer value is updated and sent over dedicated buses, then all processing elements receive the new value, but delays occur when a large number of processing elements are present
Solution Approach 1:
Instead of transmitting timer values through multiple sequential bus transactions to each processing element, the system creates copies of the timer value and distributes them through the interconnect fabric to multiple destinations simultaneously. This parallel distribution approach significantly reduces synchronization delays while ensuring all processing elements receive the updated timer value reliably.
Data Source
AI summary
Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.