Distributed Instruction Trace Architecture for Multi-Core Processors
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Solution Overview
Problem
In multi-core processor systems, the circuit overhead and bandwidth limitations of traditional trace logic units make it impractical to generate and store processor traces simultaneously across all processors, leading to inefficient use of resources and limited trace support.
Innovation Solution
The implementation of distributed instruction trace architecture, where each processor has a trace collection logic unit and a shared filtering and formatting logic unit, allows for continuous trace collection and storage of processor trace information, utilizing data compression and reduced filtering and formatting logic units to manage trace data efficiently across multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each processor has a dedicated trace logic unit with filtering and formatting capabilities, then trace collection precision and functionality are improved, but circuit overhead and device complexity increase beyond practical implementation
Solution Approach 1:
The patent segments the trace logic unit into two distinct functional components: trace collection logic units (one per processor) and shared filtering logic units (fewer in number). This segmentation allows trace collection to be distributed across all processors while concentrating the resource-intensive filtering and formatting operations in shared units, thereby reducing overall circuit overhead while maintaining trace collection precision.
Solution Approach 2:
The shared filtering logic units serve multiple processors simultaneously, performing filtering and formatting operations for trace data from multiple collection logic units. This multi-functionality reduces the total number of filtering units needed compared to having dedicated filtering units for each processor, thus reducing device complexity while maintaining comprehensive trace support.
2Productivity
If multiple trace logic units operate simultaneously, then trace data coverage and productivity are improved, but bandwidth consumption and space requirements exceed practical limitations
Solution Approach 1:
The patent merges the filtering and formatting functions into shared units that serve multiple collection logic units simultaneously. This consolidation allows simultaneous trace generation from multiple processors while sharing the bandwidth-intensive filtering and formatting operations, thereby reducing total bandwidth consumption and space requirements compared to having completely independent trace logic units for each processor.
3Device complexity
If the number of filtering and formatting logic units is reduced, then device complexity and bandwidth requirements are lowered, but trace data processing capability and measurement precision may be compromised
Solution Approach 1:
The patent implements buffering mechanisms that copy and store trace data from multiple collection logic units before processing by the shared filtering units. This copying approach allows the system to handle multiple simultaneous traces by temporarily storing data, then processing it through the shared filtering units sequentially or in batches, thereby maintaining trace data processing capability despite having fewer filtering units.
Data Source
AI summary
One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.