Distributed Video Display Clock Synchronization Control
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Solution Overview
Problem
Current distributed video display systems using system-on-chips (SOCs) suffer from clock differences and phase differences in vertical synchronizing signals, leading to screen tearing due to asynchronous playback across multiple displays.
Innovation Solution
A control apparatus connected through a network synchronizes the clocks of display chips and sets a fixed delay time to ensure synchronous playback, resetting the vSync signal to prevent screen tearing by transmitting a synchronizing signal and using a processor to manage the display frames across multiple displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each SOC operates independently with its own clock, then system complexity is reduced and ease of operation is improved, but clock phase differences accumulate over time causing display asynchronization and screen tearing
Solution Approach 1:
The patent introduces an intermediary mechanism (clock synchronization circuit and vSync signal coordination) between independent SOCs to maintain display synchronization. The intermediary mediates the clock signals and vertical synchronizing signals across multiple SOCs, allowing them to operate independently while maintaining phase alignment, thus preventing screen tearing without requiring complete clock dependency.
2Adaptability or versatility
If hardware and software configurations vary among SOCs to adapt to different applications, then adaptability is improved, but data processing differences cause frame asynchronization and increase screen tearing risks
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-configuring delay parameters for each SOC based on its specific hardware and software characteristics. Before actual video playback, the system determines the processing time differences of each SOC and sets appropriate delay values in advance. This preliminary configuration allows SOCs with different configurations to synchronize their frame output without real-time adjustment complexity.
Solution Approach 2:
The patent changes the timing parameter (delay time) for each SOC individually to compensate for differences in processing speed caused by varying hardware and software configurations. By adjusting the delay parameter, faster SOCs wait longer while slower SOCs proceed with their natural processing speed, ensuring all frames are ready simultaneously for display, thus maintaining synchronization despite configuration diversity.
3Measurement precision
If physical distribution of circuit nodes and switches is increased to support high-resolution distributed display, then display resolution is improved, but difference between center and peripheral display regions increases
Solution Approach 1:
The patent applies local quality by allowing each SOC (particularly those in peripheral regions) to have customized delay parameters and processing configurations tailored to their specific position and performance characteristics. Instead of treating all display nodes uniformly, the system adjusts local parameters at each SOC to compensate for transmission delays and processing differences, ensuring uniform display quality across the entire distributed system from center to periphery.
Data Source
AI summary
A system, a control apparatus and a control method for distributed video display are provided. The system includes an image source device configured to provide image data, a plurality of displays, a plurality of display chips respectively coupled to the displays and connected with the video source device through a network, and a control apparatus connected with the image source device and the display chips through the network and configured to transmit a playback signal to each of the display chips to control the display chips to receive the image data from the image source device and convert the received image data into display frames capable of being played by the displays. The control apparatus further transmits a synchronizing signal to each display chip to control the display chips to synchronize the clocks with each other according to the synchronizing signal and sets each of the display chips with a fixed delay time after receiving the image data to synchronously play the display frames on the displays.