Distributed Viewport Culling Engine for Parallel Graphics Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional graphics processing unit (GPU) architectures face bottlenecks in processing graphics primitives due to sequential processing and impractical data bus requirements, limiting scalability and efficiency in clipping, culling, viewport transform, and perspective correction operations.

Innovation Solution

Implementing a general processing cluster (GPC) with multiple parallel processing units, each equipped with a viewport culling engine (VPC) to perform these operations independently and in parallel, reducing the need for large data buses and enabling simultaneous processing of multiple graphics primitives.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single viewport culling engine processes all graphics primitives sequentially, then processing order is maintained, but processing throughput decreases and bottlenecks occur

Engineering Contradiction:
Improveprocessing throughputVSAvoidprocessing architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the single viewport culling engine into multiple parallel viewport culling engines (VPC0, VPC1, VPC2, VPC3), each capable of independently processing graphics primitives. This segmentation enables simultaneous processing of multiple primitive sets, dramatically increasing throughput while maintaining individual engine simplicity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If all graphics primitives are transported through a central viewport culling engine, then centralized control is achieved, but data bus size must increase impractically with more processing units

Engineering Contradiction:
Improveprocessing capacityVSAvoiddata bus size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the centralized data transport architecture into distributed data paths. Each processing cluster (TPC) has its own dedicated data bus connection to a corresponding viewport culling engine, eliminating the need for a single large bus that would require impractical size increases to support additional processing units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimension centralized bus architecture to a multi-dimensional distributed architecture where data can flow through multiple independent paths simultaneously. This dimensional change allows processing capacity to scale without proportionally increasing any single data bus size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If graphics primitives are processed in the order fetched by the data assembler, then processing simplicity is maintained, but processing efficiency decreases due to waiting for previous primitives to complete

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidsynchronization requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the sequential processing stream into multiple parallel processing streams, each handled by a dedicated viewport culling engine. This allows different sets of graphics primitives to be processed simultaneously without waiting for previous primitives to complete, significantly improving efficiency while maintaining individual stream simplicity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8704835B1Distributed clip, cull, viewport transform and perspective correction
Publication Date: 2014.04.22 NVIDIA CORP
  • US8704835B1 patent drawing
  • US8704835B1 patent drawing
  • US8704835B1 patent drawing

AI summary

A parallel processing subsystem includes a plurality of general processing clusters (GPCs). Each GPC includes one or more clipping, culling, viewport transformation, and perspective correction engines (VPC). Since VPCs are distributed per GPC, each VPC can process graphics primitives in parallel with the other VPCs processing graphics primitives.