Chip Structures with Distributed Wiring on SOI Substrates
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Solution Overview
Problem
Current chip structures with distributed wiring layouts face challenges in reducing wiring density and parasitic capacitance, which affects device performance in high-frequency applications like mobile communication devices.
Innovation Solution
The proposed solution involves forming chip structures using a silicon-on-insulator substrate with vertically separated wiring levels, where the first wiring level is coupled with source regions on the front side and the second wiring level is coupled with drain regions on the back side, utilizing a buried oxide layer to reduce wiring density and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring is distributed across multiple levels in conventional chip structures, then wiring density is reduced, but parasitic capacitance remains high due to proximity of wiring levels
Solution Approach 1:
The patent utilizes the vertical dimension by forming first wiring on the front surface and second wiring on the back surface of the substrate, separated by the substrate thickness. This three-dimensional distribution of wiring levels increases the vertical separation distance, thereby reducing parasitic capacitance between wiring levels while effectively distributing wiring across the chip structure.
Solution Approach 2:
The patent segments the wiring into distinct first wiring and second wiring located on opposite surfaces of the substrate. This segmentation separates the wiring into different spatial zones, reducing the density of wiring in any single plane and decreasing the capacitive coupling between adjacent wiring elements.
2Object-generated harmful factors
If wiring levels are vertically separated using buried oxide layer, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The substrate itself serves as the separation medium between the first and second wiring levels. The inherent thickness and material properties of the substrate provide the necessary vertical separation to reduce parasitic capacitance, eliminating the need for additional dedicated separation structures or complex multi-layer dielectric systems.
Solution Approach 2:
The substrate performs multiple functions: it serves as the mechanical support for the device, provides electrical isolation between front and back surface wiring, and acts as the separation medium that reduces parasitic capacitance. This multi-functionality simplifies the overall structure by combining several roles into a single component.
Data Source
AI summary
Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.