Distributed Workload Parser for GPU Compute Tracking
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Solution Overview
Problem
Distributed processing architectures for GPUs face challenges in efficiently distributing and tracking compute workloads across multiple shader cores, leading to potential overburdening of communication fabrics and reduced performance due to limited information availability compared to centralized parsers.
Innovation Solution
A distributed hierarchical workload parser architecture that includes global and distributed workload parsers, completion aggregator circuitry, and shader FIFOs to efficiently distribute and track workgroup completions, aggregating and reporting multiple completions in a single clock cycle, thereby reducing bandwidth use and improving fairness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a distributed processing architecture is used to increase compute power, then processing capability is improved, but tracking and distributing compute workloads becomes more complex
Solution Approach 1:
The patent divides the monolithic workload parser into multiple distributed workload parsers, each responsible for a subset of shader cores. This segmentation allows the system to scale compute power while maintaining manageable complexity at each parser node, as each parser only needs to track workloads for its assigned shaders rather than all shaders system-wide.
Solution Approach 2:
The patent introduces a hierarchical dimension to workload tracking by organizing parsers in levels (e.g., first-level parsers for groups of shaders, second-level parsers for aggregate tracking). This dimensional organization allows the system to track complex distributed workloads by breaking down the tracking task across multiple hierarchical levels rather than requiring a single complex tracking mechanism.
2Productivity
If more shader cores are activated to process workloads, then compute throughput is improved, but bandwidth consumption increases
Solution Approach 1:
The patent combines completion signals from multiple shader cores into aggregated completion indicators that are processed by the workload parser. Instead of each shader core generating separate completion signals that consume individual bandwidth resources, the system merges these signals into consolidated updates, reducing overall bandwidth consumption while maintaining accurate tracking of all shader completions.
Solution Approach 2:
The patent uses replicated data structures (such as copy-in-copy-out buffers) that allow multiple shader cores to write completion information to shared memory regions without requiring constant communication overhead. Each shader core can update its completion status by writing to a pre-allocated buffer region, eliminating the need for repeated read-modify-write operations and reducing bandwidth usage.
3Adaptability or versatility
If workload information is distributed across multiple parsers, then processing scalability is improved, but information availability for tracking decreases
Solution Approach 1:
The patent implements feedback mechanisms where distributed workload parsers continuously exchange completion information and update their local state. Each parser receives feedback about workload completion from its assigned shader cores and propagates this information to other parsers through the inter-parser communication interface, ensuring that all parsers maintain an accurate view of overall system state despite the distributed architecture.
Solution Approach 2:
The patent designs the distributed workload parser architecture with universal data structures and communication protocols that can handle any distribution of shader cores across parsers. The completion aggregator and inter-parser interface are designed to work regardless of how many parsers exist or how shaders are distributed among them, maintaining full information availability through a standardized universal interface that works for any system configuration.
Data Source
AI summary
Techniques are disclosed relating to tracking compute workgroup completions in a distributed processor. In some embodiments, an apparatus includes a plurality of shader processors configured to perform operations for compute workgroups included in compute kernels, a master workload parser circuit, a plurality of distributed workload parser circuits, and a communications fabric connected to the plurality of distributed workload parser circuits and the master workload parser circuit. In some embodiments, a distributed workload parser circuit is configured to maintain, for each of a set of the shader processors, a data structure that specifies a count of workgroup completions for one or more kernels processed by the shader processor, determine, for the set of shader processors based on counts of workgroup completions for a first kernel, an aggregate count of completions to report for the first kernel, send the aggregate count to the master workload parser circuit over the communications fabric, and adjust the data structures to reflect counts included in the aggregate count.