Distributed Write Destaging Across Boards to Reduce Array Latency

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Solution Overview

Problem

Current message-passing techniques in storage arrays increase latency and consume significant memory resources when destaging data, leading to inefficient data management.

Innovation Solution

Implementing a distributed storage system with shared local and board-level memories, local synchronous write destage queues, and a destage controller that balances IO workloads across boards based on performance-related hyperparameters, reducing the need for message passing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If message-passing techniques are used for data destaging in storage arrays, then data can be transferred between boards, but latency increases and memory resources are consumed

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the destaging functionality into the target board itself, eliminating the need for message passing between boards. The target board performs destaging operations locally using its own resources, combining data reception and destaging functions in one location to reduce latency and memory consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the destaging operation from the source board and performs it directly at the target board. This removes the intermediate message-passing step and associated memory requirements, allowing the target board to directly write received data to storage devices without requiring additional memory buffers for message transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If message-passing techniques are used for data destaging in storage arrays, then data can be transferred between boards, but memory resources are consumed

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidmemory resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the destaging operation from the source board and performs it directly at the target board. This removes the intermediate message-passing step and associated memory requirements, allowing the target board to directly write received data to storage devices without requiring additional memory buffers for message transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The target board performs destaging operations autonomously using its own local resources. Each board serves itself by having the capability to destage data locally, eliminating the need for dedicated message buffers and reducing overall memory resource consumption in the system.

Inventive Principle:
Principle #25Self-service

3Device complexity

If write destaging is centralized in storage arrays, then data management is simplified, but performance and scalability are limited

Engineering Contradiction:
Improvedata management complexityVSAvoiddata management efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the destaging function from a centralized location and distributes it across multiple target boards. Each board independently performs destaging operations for data it receives, creating a distributed architecture that improves performance and scalability while maintaining manageable complexity through standardized local operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local destaging capability at each target board, allowing each board to optimize its own destaging operations based on local conditions. This local quality approach enables parallel processing across multiple boards, improving overall productivity while keeping each board's complexity manageable.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12360674B2Distributed write destaging
Publication Date: 2025.07.15 DELL PROD LP
  • US12360674B2 patent drawing
  • US12360674B2 patent drawing
  • US12360674B2 patent drawing

AI summary

One or more aspects of the present disclosure relate to distributing write destaging amongst a storage array's boards. In embodiments, an input/output (IO) workload is received at a storage array. In addition, a write IO request in the IO workload is directed to a target board of a plurality of boards of the storage array based on one or more performance-related hyperparameters of each board. Further, write data of the write IO request to a storage device is destaged by the target board.