Distributed Write Drivers for MRAM Bitline Resistance
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Solution Overview
Problem
Advanced CMOS process technology integrated STT-MRAMs face high voltage and high current-density issues during programming, leading to insufficient drive current, high write error rates, and low speed switching, which worsen as CMOS process scales to lower metal pitches.
Innovation Solution
The implementation of embedded write drivers on BitLine (BL) and SourceLine (SL) in MRAM arrays, with distributed local write drivers and end drivers, allows for improved drive current to MTJ devices without causing stress, reducing write error rates and enhancing switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If STT-MRAM is integrated with advanced CMOS process technology to achieve higher memory density, then memory density is improved, but drive current becomes insufficient due to intrinsic high resistance of the MRAM device during write operation
Solution Approach 1:
The patent divides the write driver functionality into multiple distributed local write drivers positioned at different locations along the bitline and sourceline, rather than using a single centralized driver. This segmentation allows each local driver to provide targeted current boosting to nearby memory cells, overcoming the high resistance issue without requiring excessive total current that would cause overdriving near the write driving circuitry.
Solution Approach 2:
The patent introduces alternative bitlines and sourcelines as intermediary conductive paths with lower resistance compared to the regular bitlines and sourcelines. These alternative paths serve as mediators to deliver write current more efficiently to the MTJ devices, reducing the overall resistance in the current path and improving drive current without increasing stress on the MTJ devices.
2Speed
If write current is increased to overcome high resistance and improve write speed, then switching speed is improved, but write error rates increase due to overdriving of bits near the write driving circuitry
Solution Approach 1:
By segmenting the write driver into multiple distributed local drivers, each driver operates at lower current levels locally, avoiding the overdriving problem that occurs with a single high-current centralized driver. This segmentation maintains fast switching speed while reducing write errors through controlled current distribution.
Solution Approach 2:
The patent applies different current driving characteristics to different regions of the memory array through distributed local write drivers. Each local driver provides appropriate current levels tailored to its specific location and the resistance characteristics of nearby memory cells, ensuring reliable writing without overdriving any particular region.
3Use of energy by moving object
If distributed local write drivers are implemented to improve current distribution, then drive current is improved, but device complexity increases
Solution Approach 1:
The distributed local write drivers are designed to perform multiple functions: they provide current boosting for write operations, serve as read drivers for read operations, and can function as keepers to maintain signal levels. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity despite the distributed architecture.
Solution Approach 2:
The patent merges the write driver and read driver functionalities into a single distributed local driver structure. By combining these functions, the patent avoids duplicating circuitry and reduces overall device complexity while still achieving improved current distribution for write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves write current distribution across all memory cells, reducing stress on MTJ devices, lowering write error rates, and accelerating switching speed while maintaining reliability.
Implementation Method 1
STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) integrated with advanced CMOS
Data Source
AI summary
Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.