Network of Distributor Circuits for Dynamic Message Routing
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Solution Overview
Problem
Existing systems for task distribution in processing circuits often experience bottlenecks, particularly in highly distributed environments where small tasks are processed, leading to inefficiencies and delays, as a single task distribution device can become a bottleneck when handling many tasks simultaneously.
Innovation Solution
A network of distributor circuits is used to select processing circuits based on their current message handling ability, allowing messages to be forwarded dynamically across multiple paths, avoiding the need for predetermined processing circuit associations and minimizing bottlenecks by distributing tasks across multiple distributor circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single task distribution device is used to distribute tasks from multiple source circuits to multiple processing circuits, then the system structure is simple, but the task distribution device becomes a bottleneck when handling many small tasks simultaneously
Solution Approach 1:
The single task distribution device is segmented into multiple distributor circuits that operate in parallel. Each distributor circuit handles a subset of the task distribution, eliminating the bottleneck of a single device while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The system transitions from a single-point distribution architecture to a multi-dimensional distributed architecture where multiple distributor circuits operate simultaneously across different dimensions of the task flow, increasing throughput without proportionally increasing complexity.
2Productivity
If multiple task distribution devices are used in parallel to reduce bottlenecks, then task distribution throughput increases, but processor utilization becomes suboptimal when many tasks are handled by one device and few by others
Solution Approach 1:
The distributor circuits dynamically adapt their task distribution based on real-time processor availability and load conditions. This dynamic behavior allows the system to balance workload across processors efficiently, ensuring optimal utilization while maintaining high throughput.
Solution Approach 2:
The system implements feedback mechanisms where distributor circuits monitor processor status and adjust their distribution patterns accordingly. This feedback loop ensures that tasks are evenly distributed across available processors, preventing both bottlenecks and underutilization.
3Ease of operation
If each task source is coupled to its own set of processors, then task distribution is simple, but processor utilization is inefficient when task production rates vary significantly between sources
Solution Approach 1:
The distributor circuits are designed with universal functionality to handle tasks from any source circuit and route them to any available processing circuit. This multi-functional approach maintains operational simplicity while enabling flexible task distribution that optimizes processor utilization regardless of varying task production rates.
Data Source
AI summary
Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.