Disturb-Free Circuit for Non-Volatile Memory Write Verification
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Solution Overview
Problem
Write disturbances in non-volatile memory can cause data stored in un-selected cells to be disturbed during a write operation, leading to data corruption and requiring a method to verify and compensate for such disturbances.
Innovation Solution
A storage device with a disturb-free circuit that performs a verification operation on un-selected cells after a write operation to determine if data has been disturbed, and if so, performs a second write operation to restore the data, using a specific conductive line to couple the selected and un-selected cells for verification and compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a write operation is performed on non-volatile memory, then data is written to the selected cell, but data stored in un-selected cells may be disturbed by the write operation
Solution Approach 1:
The patent performs a verification operation on un-selected cells immediately after a write operation to detect disturbances before they cause data corruption. By proactively checking the state of un-selected cells that share the same conductive line with the selected cell, the system can identify and compensate for write disturbances before they propagate, thus maintaining data integrity without significantly impacting write speed.
Solution Approach 2:
The patent implements a feedback mechanism where the verification operation results are used to determine whether a compensation operation is needed. If the verification operation detects that data in un-selected cells has been disturbed, the system automatically performs a compensation write operation to restore the data. This closed-loop feedback approach ensures data integrity while minimizing unnecessary operations that would slow down the write process.
2Reliability
If verification operations are performed on all un-selected cells, then data integrity is improved, but power consumption and operation time increase
Solution Approach 1:
The patent applies verification operations selectively only to un-selected cells that are coupled to the same conductive line as the selected cell, rather than performing verification on all un-selected cells in the memory array. This localized approach focuses verification resources on the specific cells that are at risk of write disturbance, thereby maintaining data integrity for affected cells while minimizing the power consumption and time associated with verifying cells that are not at risk.
3Reliability
If verification operations are performed on all un-selected cells, then data integrity is improved, but operation time increases
Solution Approach 1:
The patent limits verification operations to only those un-selected cells that share a conductive line with the selected cell undergoing the write operation. This targeted verification approach reduces the number of cells that need to be checked, thereby minimizing the additional time required for verification and compensation operations while still ensuring data integrity for the cells that are actually at risk of write disturbance.
Solution Approach 2:
The patent performs verification operations on a partial set of un-selected cells (those coupled to the same conductive line) rather than all un-selected cells. This partial action is sufficient to detect and compensate for write disturbances that can occur through conductive line coupling, while avoiding the excessive time penalty that would result from verifying the entire memory array.
Data Source
AI summary
A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.