Serial Data Receiver Dither Assisted Equalization
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Solution Overview
Problem
In high-speed communication systems, wide-range channel equalizer circuits with high gain can cause saturation issues when used for low-loss channels, leading to inaccurate sampling due to the amplitude of received signals exceeding the dynamic range of digital-to-analog converter (DAC) circuits, especially when receiving PAM3 and PAM4 encoded signals.
Innovation Solution
The integration of a dither circuit that combines time-varying signals with sampled signals to limit saturation of the DAC and reduce inaccurate sampling results, by generating a dither signal when the DAC is saturated, allowing the equalization to remain within the dynamic range and preventing saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wide-range channel equalizer circuits with high gain are used, then signal equalization performance is improved, but DAC saturation occurs leading to inaccurate sampling
Solution Approach 1:
The patent applies preliminary anti-action by detecting potential DAC saturation conditions before they occur and preemptively adjusting the equalizer gain or activating clipping prevention mechanisms. The system monitors the equalized signal amplitude and compares it against the DAC's dynamic range limits, then reduces gain or applies soft clipping before the signal enters the saturation region, preventing inaccurate sampling from occurring in the first place
Solution Approach 2:
The patent implements dynamics by making the equalizer gain adaptive rather than fixed. The system continuously adjusts the equalizer parameters based on the received signal characteristics and channel conditions, dynamically optimizing the balance between equalization performance and avoiding DAC saturation. This includes adaptive gain control and variable clipping thresholds that respond to real-time signal levels
2Adaptability or versatility
If high gain equalization is applied, then low-loss channel performance is improved, but DAC saturation occurs
Solution Approach 1:
The patent applies preliminary action by performing channel characterization and equalizer parameter optimization during a training phase before actual data transmission. The system pre-computes the optimal equalizer settings for different channel conditions and stores them for quick retrieval, allowing the receiver to adapt to low-loss channels without requiring high gain during normal operation, thus preventing DAC saturation
Solution Approach 2:
The patent applies partial action by using just enough equalization gain to compensate for channel losses without over-equalizing. The system carefully controls the equalizer strength to achieve sufficient signal recovery while maintaining the output within the DAC's linear range, avoiding the excessive gain that would cause saturation in low-loss channel conditions
Data Source
AI summary
To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.