Dithered Clock Divider for Fine-Grained Frequency Scaling
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Solution Overview
Problem
Existing clock frequency dividers in semiconductor circuits face challenges in efficiently generating clock signals with reduced frequencies while maintaining phase alignment, reducing power consumption, and minimizing latency and data corruption, especially in high-speed serial links and PLL feedback paths.
Innovation Solution
The implementation of clock frequency dividers with a clock gating circuit and a control circuit that receive a configurable input clock frequency reduction factor, allowing for a reduced clock rate with a smallest granularity of 1/M of the input clock frequency, using an M-bit pattern or ratio of N to M to determine the output clock signal's assertion and negation cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a clock frequency divider is used to generate output clock signals with reduced frequency, then the clock frequency is reduced, but the PLL locking latency increases and phase alignment is affected
Solution Approach 1:
The patent implements a dynamic clock frequency divider that can be reconfigured to change division ratios on-the-fly. The control logic receives dynamic control signals that adjust the division ratio without requiring PLL re-locking, allowing the system to adapt clock frequencies dynamically while maintaining phase alignment and minimizing locking latency.
Solution Approach 2:
The clock frequency divider is segmented into multiple independent division stages with individual control logic for each stage. This segmentation allows different parts of the divider to operate independently with different division ratios, enabling fine-grained frequency control without affecting the entire PLL locking process.
2Reliability
If sequential circuits are used to synchronize data signals, then data synchronization is achieved, but power consumption increases and metastability may occur
Solution Approach 1:
The patent employs periodic clock gating that enables sequential circuits only during specific clock cycles when data synchronization is actually needed. By periodically enabling/disabling clock signals to sequential elements based on control logic, the system maintains synchronization reliability while significantly reducing power consumption during idle periods.
Solution Approach 2:
The control logic automatically detects when synchronization is needed and activates the appropriate sequential circuits without external intervention. The system self-manages the enabling/disabling of sequential elements based on data flow requirements, optimizing power consumption while maintaining synchronization.
3Device complexity
If a fixed clock frequency divider is used, then circuit simplicity is maintained, but adaptability to different frequency ranges is limited
Solution Approach 1:
The patent implements a dynamic clock frequency divider with reconfigurable division ratios controlled by control logic that receives configuration signals. The divider can be programmed to support multiple frequency ranges and division ratios, providing high adaptability while maintaining relatively simple circuit architecture through systematic design.
Solution Approach 2:
The clock frequency divider is designed as a universal module that can operate with multiple division ratios and support various frequency ranges. The same basic circuit structure can be configured for different applications by changing control signals, eliminating the need for multiple dedicated dividers for different frequency ranges.
Data Source
AI summary
An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.