Dithered Ring Oscillator for Critical Path Delay Matching
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Solution Overview
Problem
Existing power management systems for digital circuitry in computing devices face challenges in dynamically matching the propagation delay of critical path circuits with ring oscillators, as a static number of inverter elements cannot achieve desired ratios, leading to inefficiencies in power consumption regulation.
Innovation Solution
The implementation of dither circuitry that periodically adjusts the number of inverter elements in a ring oscillator to match the average propagation delay of a critical path circuit, using a multiplexer controlled by a counter to selectively remove elements and configure the oscillator, allowing for dynamic adjustment of the propagation delay relative to the critical path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a static number of inverter elements is used in the ring oscillator, then the hardware complexity is reduced, but the propagation delay cannot be dynamically matched to the critical path circuit
Solution Approach 1:
The patent applies dynamics by making the number of inverter elements in the ring oscillator adjustable rather than fixed. The dither circuitry periodically varies the number of active inverter elements, allowing the propagation delay to be dynamically matched to the critical path circuit's propagation delay, thereby resolving the contradiction between adaptability and hardware complexity.
Solution Approach 2:
The dither circuitry implements periodic action by cyclically adjusting the number of inverter elements in the ring oscillator. This periodic variation allows the system to achieve an average propagation delay that matches the critical path circuit while using a relatively simple static hardware structure, thus resolving the contradiction between adaptability and hardware complexity.
2Measurement precision
If the number of inverter elements is increased to achieve better propagation delay matching, then the propagation delay matching improves, but the power consumption increases
Solution Approach 1:
The dither circuitry uses periodic action to cyclically adjust the number of inverter elements, achieving precise propagation delay matching through time-averaged behavior rather than requiring a large static number of elements. This reduces power consumption while maintaining measurement precision in propagation delay matching.
Solution Approach 2:
The system changes the parameter of the number of active inverter elements dynamically to optimize propagation delay matching. By varying this parameter periodically rather than using a large fixed number of elements, the system achieves precise matching with lower power consumption.
3Adaptability or versatility
If dither circuitry is added to periodically adjust inverter elements, then propagation delay matching is achieved, but device complexity increases
Solution Approach 1:
The dither circuitry implements dynamics by periodically adjusting the number of active inverter elements, enabling propagation delay matching while keeping the overall circuit structure relatively simple. The dynamic adjustment is achieved through straightforward control logic that cycles through different numbers of active elements.
Solution Approach 2:
The dither circuitry uses periodic action with simple control logic to adjust inverter elements, achieving propagation delay matching without requiring complex continuous control mechanisms. The periodic nature of the adjustment simplifies the control circuitry while still achieving the desired adaptability.
Data Source
AI summary
A computing device is disclosed comprising digital circuitry including a critical path circuit, and a gate speed regulator. A ring oscillator generates an oscillation frequency, and dither circuitry periodically adjusts a number of inverter elements in the ring oscillator in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit. A comparator compares the oscillation frequency to a reference frequency to generate an error signal, and an adjustable circuit, responsive to the error signal, adjusts at least one of a supply voltage and a clocking frequency applied to the digital circuitry.