Divide-by-1.5 Circuit Using Divide-by-3 and PLL Frequency Doubling
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Solution Overview
Problem
Fractional divider circuits, particularly those requiring a 50% duty cycle, are complex and contribute to power dissipation and area consumption on integrated circuit chips due to their phase-locked loop (PLL) circuitry.
Innovation Solution
A divide-by-1.5 circuit is implemented using a divide-by-3 circuit and a PLL-based frequency doubler circuit, where the output of the divide-by-3 circuit is coupled to the input of the frequency doubler, reducing circuit complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fractional divider circuit is implemented using phase-locked loop (PLL) circuitry to achieve a 50 percent duty cycle, then the duty cycle requirement is met, but circuit complexity and area consumption increase
Solution Approach 1:
The fractional divider circuit is segmented into multiple functional blocks: a divide-by-3 circuit using flip-flops, a frequency doubler circuit, and a multiplexer. This segmentation allows each block to perform a specific function with simpler circuitry, avoiding the need for a single complex PLL-based fractional divider while still achieving the 50% duty cycle requirement.
Solution Approach 2:
The circuit uses a multiplexer to dynamically select between different divide-by-1.5 circuit implementations based on operating conditions. This dynamic selection allows the system to optimize between speed and power consumption, maintaining 50% duty cycle while adapting to different performance requirements without permanently committing to a complex PLL design.
2Ease of operation
If a fractional divider circuit is implemented using phase-locked loop (PLL) circuitry to achieve a 50 percent duty cycle, then the duty cycle requirement is met, but power dissipation increases
Solution Approach 1:
The multiplexer enables dynamic selection between different circuit implementations optimized for different power consumption levels. By switching between divide-by-1.5 circuit options based on operating conditions, the system can minimize power dissipation while maintaining the required 50% duty cycle, avoiding continuous operation of power-intensive PLL circuitry.
Solution Approach 2:
The circuit changes operational parameters by selecting different divide-by-1.5 implementations through the multiplexer. This allows the system to adjust power consumption levels while maintaining the same functional output (50% duty cycle frequency division), effectively managing power dissipation based on operational requirements.
3Adaptability or versatility
If multiple frequency divider circuits are included to handle different operating conditions, then adaptability is improved, but device area consumption increases
Solution Approach 1:
The frequency division functionality is segmented into specialized circuits (divide-by-3, frequency doubler) that work together through a multiplexer. This segmentation allows efficient use of chip area by reusing common components and only instantiating necessary circuitry for specific divide-by-1.5 operations, rather than implementing all possible frequency dividers simultaneously.
Solution Approach 2:
The divide-by-3 circuit and frequency doubler are designed as universal building blocks that can be combined in different configurations to achieve frequency division with 50% duty cycle. The multiplexer provides a universal interface that can select between different implementations, allowing the same hardware resources to serve multiple operating conditions without requiring separate dedicated circuits for each scenario.
Data Source
AI summary
A divide-by-1.5 circuit includes a divide-by-3 circuit that and a frequency doubler circuit. The divide-by-3 circuit has few logic elements and provides glitch-free operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phase-locked loop circuitry.