Inductor-Less Divide-by-3 Frequency Divider With Edge-Retimed Injection
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Solution Overview
Problem
Injection-locked frequency dividers face challenges in maintaining a constant duty cycle and reducing jitter when dividing frequencies, particularly when the divisor value is odd, leading to asymmetries and timing errors.
Innovation Solution
The frequency divider modifies the injection of the input signal into the oscillator based on the logic states of the oscillator nodes, using multiplexers to alternate between rising and falling edges of the input signal to ensure consistent retiming and balanced injection, thereby maintaining a stable frequency-divided output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional injection-locked frequency divider is used to divide frequency, then the output frequency is reduced to 1/N times the input frequency, but duty cycle errors and jitter increase particularly when N is odd
Solution Approach 1:
The patent applies preliminary action by injecting the input signal into the oscillator at specifically predetermined timing moments before the desired output edges. The retiming circuit determines optimal injection timing based on oscillator state, ensuring that the injection occurs at the most effective moment to minimize duty cycle errors and jitter before they can propagate through the delay elements.
Solution Approach 2:
The patent implements feedback through the retiming circuit that monitors the oscillator nodes and dynamically adjusts the injection timing of the input signal. The retiming circuit uses the state of oscillator nodes to generate retiming signals that control when injection occurs, creating a closed-loop system that compensates for duty cycle errors and maintains stable output despite variations in oscillator behavior.
2Reliability
If the input signal is injected continuously into the oscillator, then the oscillator remains locked to the input frequency, but jitter and duty cycle errors accumulate
Solution Approach 1:
The patent applies periodic action by injecting the input signal at discrete, periodic intervals rather than continuously. The retiming circuit generates injection pulses at specific periods based on the oscillator's state, creating a rhythmic injection pattern that resets timing errors periodically while maintaining lock stability. This periodic resetting prevents jitter and duty cycle errors from accumulating over time.
Solution Approach 2:
The injection occurs at predetermined moments before the desired output edges are generated, allowing the oscillator to be reset to a known good state before critical output transitions. This preliminary injection timing ensures that duty cycle errors are corrected before they propagate to the final output, maintaining timing accuracy without requiring continuous injection.
3Productivity
If multiple delay elements are used in the oscillator to achieve frequency division, then the frequency division ratio increases, but asymmetries in odd-divisor configurations cause timing errors
Solution Approach 1:
The patent applies local quality by treating different phases of the oscillation cycle differently through phase-selective injection. The retiming circuit identifies specific oscillator nodes and injection timing moments that are most critical for maintaining symmetry, applying correction locally at these strategic points rather than uniformly across all delay elements. This targeted approach compensates for asymmetries in odd-divisor configurations.
Solution Approach 2:
The patent addresses asymmetry by intentionally introducing controlled asymmetric injection timing based on the detected oscillator state. The retiming circuit generates different injection timing offsets for different phases of the oscillation cycle, creating a deliberate asymmetric correction that counteracts the inherent asymmetries in odd-divisor frequency division. This controlled asymmetry in injection timing restores overall symmetry to the output waveform.
Data Source
AI summary
A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.