Combined Divide-Square Root Circuitry with Shared Remainder Updating
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Solution Overview
Problem
Existing data processing systems require significant additional circuitry for the SRT square root algorithm, which slows down the SRT division algorithm and compromises the performance of combined divide-square root circuitry.
Innovation Solution
Implementing shared remainder updating circuitry that performs a greater number of iterations per processing cycle for the SRT division algorithm than for the SRT square root algorithm, allowing for greater sharing of circuitry and reducing the need for extra circuitry, thus maintaining the performance of the SRT division algorithm while optimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional circuitry is provided for the SRT square root algorithm, then the square root operation can be performed, but the division algorithm performance is slowed down and circuit area increases
Solution Approach 1:
The patent combines the SRT division algorithm and SRT square root algorithm into a single unified circuit structure. The remainder updating circuitry is shared between both algorithms, allowing the system to perform both division and square root operations without requiring separate dedicated circuitry for each operation. This merging approach enables the square root capability to be added while maintaining division performance by using the same hardware resources for both functions.
Solution Approach 2:
The unified circuit structure is designed to perform multiple functions - both SRT division and SRT square root operations. The remainder updating circuitry serves as a universal component that can be utilized by either algorithm depending on the operation being executed. This multi-functionality allows the system to achieve versatility (performing both operations) without the penalty of duplicated circuitry that would otherwise slow down division operations.
2Adaptability or versatility
If additional circuitry is provided for the SRT square root algorithm, then the square root operation can be performed, but circuit area increases
Solution Approach 1:
The patent merges the circuitry for SRT division and SRT square root algorithms into a single unified structure. By combining the remainder updating circuitry used in both algorithms, the system avoids duplicating hardware components. This merging significantly reduces the total circuit area required compared to providing separate dedicated circuitry for each operation, while still enabling both division and square root capabilities.
Solution Approach 2:
The unified circuit structure implements universal remainder updating circuitry that can serve both SRT division and SRT square root operations. This multi-functional design eliminates the need for additional dedicated circuitry for square root operations, thereby minimizing circuit area expansion while achieving the desired versatility of supporting both mathematical operations.
3Area of stationary object
If the same number of iterations per processing cycle is used for both algorithms, then circuit sharing is maximized, but division algorithm performance is compromised
Solution Approach 1:
The patent implements a dynamic iteration scheme where the number of iterations per processing cycle varies depending on the algorithm being executed. For SRT division operations, the system performs a greater number of iterations per processing cycle compared to SRT square root operations. This dynamic adjustment allows the division algorithm to maintain high performance by utilizing more iterations when needed, while still sharing the same circuitry for square root operations with fewer iterations, thus avoiding the performance compromise that would result from limiting all operations to the same iteration count.
Data Source
AI summary
A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.