Bias Circuit for Divided Bit Lines in CMOS Image Sensors
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Solution Overview
Problem
The frame rate of image sensors is limited by the bit line settling time, which is influenced by the capacitance of the bit lines, and existing technologies have not effectively addressed this limitation.
Innovation Solution
Dividing bit lines into separate portions that are electrically separated from each other, reducing the capacitance of each portion and thereby shortening the bit line settling time, allowing for improved frame rates in CMOS image sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If bit lines are divided into separate portions, then bit line settling time is reduced, but device complexity increases
Solution Approach 1:
The bit line is divided into multiple separate portions (first bit line portion and second bit line portion) that are electrically isolated from each other. This segmentation reduces the total capacitance of each bit line portion, thereby reducing the settling time required for each portion to stabilize after a signal transition. The patent applies segmentation by physically separating the bit line into discrete segments with isolation structures between them.
2Productivity
If bit lines are divided into separate portions, then frame rate is improved, but manufacturing complexity increases
Solution Approach 1:
The bit line is segmented into multiple electrically isolated portions, which reduces the capacitance of each segment and consequently reduces the settling time. This enables higher frame rates in CMOS image sensors. The segmentation is implemented through physical separation with isolation structures that can be integrated into the existing CMOS fabrication process.
Solution Approach 2:
An isolation structure (intermediary element) is introduced between the first and second bit line portions to prevent electrical interaction between them. This intermediary structure enables the bit line to be divided into independent segments while maintaining physical continuity in the substrate, allowing reduced capacitance per segment without complete discontinuity of the bit line structure.
3Loss of time
If bit line capacitance is reduced, then bit line settling time is reduced, but signal integrity may deteriorate
Solution Approach 1:
The bit line is divided into multiple segments with reduced individual capacitance values. Each segment settles faster independently, improving the overall settling time performance. The segmentation is designed such that each portion maintains sufficient signal strength while the reduced capacitance enables faster settling.
Solution Approach 2:
An isolation structure is positioned between bit line portions to prevent capacitive coupling and electrical interference between segments. This intermediary element ensures that signals on one bit line portion do not interfere with adjacent portions, maintaining signal integrity while enabling independent settling of each segment.
Data Source
AI summary
An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.