Divided Bitline Flash Memory Array with Local Sense
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Solution Overview
Problem
Conventional flash memory arrays face inefficiencies in read operations due to long RC delay times, which hinder performance and speed, especially when dealing with multiple memory segments.
Innovation Solution
The implementation of a flash memory array with divided bitlines and a data handling system that includes multiple data handlers, allowing for pre-charging, sensing, and sequential transmission of read data through a network of data handlers to reduce RC delay by optimizing bitline usage and voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional flash memory arrays use unified bitlines for multiple memory segments, then device complexity is reduced, but RC delay time increases significantly
Solution Approach 1:
The bitline structure is divided into multiple independent bitline groups, with each group serving a specific memory segment. This segmentation allows parallel operation of bitlines across different segments, reducing the overall RC delay time while maintaining manageable device complexity through modular organization.
Solution Approach 2:
The patent introduces a hierarchical dimension to the bitline structure by organizing bitlines into groups that serve different memory segments at different levels. This multi-level hierarchical organization enables simultaneous signal transmission across multiple segments, effectively reducing RC delay without proportionally increasing complexity.
2Quantity of substance
If flash memory arrays increase the number of memory segments, then storage capacity increases, but read operation time increases due to longer RC delay
Solution Approach 1:
By dividing the memory array into multiple segments with dedicated bitline groups, the patent enables independent and parallel read operations across segments. This allows storage capacity to scale with segment count while read operation time remains constrained by the smaller RC delay of individual segment bitlines rather than the entire array.
Solution Approach 2:
The divided bitline structure enables continuous parallel read operations across multiple memory segments simultaneously. While one segment is being read, other segments can undergo preparation or other operations, maintaining continuous productive activity and reducing overall access time for multi-segment memory systems.
Data Source
AI summary
A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache.