Divided Capacitor Bridge Layout for Leakage-Safe GIP Displays
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Solution Overview
Problem
In GIP-type display devices, fine leakage occurs during power supply due to the lack of an overlay margin between the source/drain and gate metal layers, and voltage drops at the GIP charging node during sensing operations, leading to output noise.
Innovation Solution
The display device is designed with a bridge line that connects neighboring divided capacitors, where the source and drain metal is formed at the top layer and the gate metal is inwardly located at the lower layer with an insulating layer in between, maintaining a certain spacing to prevent leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the source/drain metal and gate metal are closely positioned to form the capacitor, then the capacitor area is reduced, but fine leakage occurs during power supply due to lack of overlay margin
Solution Approach 1:
The patent introduces a vertical dimension by stacking the source/drain metal layer and gate metal layer in different levels, connected through via holes. This three-dimensional arrangement reduces the planar area occupation while maintaining sufficient spacing between metal layers to prevent leakage, thus resolving the contradiction between area reduction and reliability.
Solution Approach 2:
The patent introduces insulating layers (first insulating layer and second insulating layer) as intermediaries between the source/drain metal and gate metal. These insulating layers provide electrical isolation and prevent direct contact between the metal layers, eliminating the leakage path while allowing close positioning for area efficiency.
2Ease of manufacture
If the bridge line structure is simplified, then the manufacturing process is easier, but voltage drop occurs at the GIP charging node during sensing operations
Solution Approach 1:
The bridge line is segmented into multiple conductive portions (first bridge line and second bridge line) with insulating layers between them. This segmentation allows each segment to be independently optimized for electrical performance while maintaining manufacturing simplicity through standardized layering processes.
Solution Approach 2:
The patent applies different structural characteristics to different portions of the bridge line. The first bridge line portion has the source/drain metal configuration while the second bridge line portion has the gate metal configuration, with insulating layers strategically placed. This local differentiation optimizes voltage stability at critical nodes while keeping the overall structure manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents fine leakage during power supply and eliminates output noise by maintaining normal charging operations of the divided capacitors during sensing operations.
Implementation Method 1
the S/D metal and the gate metal form the capacitor with an insulating layer interposed therebetween
Implementation Method 2
The capacitor area includes at least one or more divided capacitors for maintaining power supplied to such transistor area
Data Source
AI summary
A display device includes a display panel having a display area and a non-display area, at least one thin-film transistor disposed in the non-display area, at least two or more divided capacitors disposed in the non-display area, and a bridge line for connecting two neighboring divided capacitors with each other among the at least two or more divided capacitors. The non-display area includes a light-blocking film disposed on a substrate and having a stepped first region and a flat second region, and a buffer and gate insulating film disposed on the light-blocking film, and having a bent first region disposed on the stepped first region of the light-blocking layer and a flat second region disposed on the flat second region of the light-blocking layer.


