Divided Clock Synchronization for Accurate IC Command Decoding
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Solution Overview
Problem
Integrated circuits face challenges in accurately synchronizing external command signals with high-frequency external clock signals, leading to inaccurate command recognition and increased power consumption during synchronization operations.
Innovation Solution
The integrated circuit employs a clock generation circuit to divide external clock signals into low-frequency divided clock signals, which are then used by a command generation circuit to synchronize and decode external command signals with a chip select signal, thereby improving synchronization accuracy and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the external clock signal frequency is increased to improve operating speed, then the operating speed of the integrated circuit is improved, but the synchronization accuracy of the external command signal deteriorates
Solution Approach 1:
The patent divides the high-frequency external clock signal into multiple lower-frequency divided clock signals using a clock generation circuit. This segmentation allows the command generation circuit to synchronize external command signals using the lower-frequency divided clock signals, thereby maintaining synchronization accuracy while the overall circuit operates at high speed using the original external clock signal.
2Speed
If the external clock signal frequency is increased to improve operating speed, then the operating speed of the integrated circuit is improved, but the power consumption increases due to increased toggling operations
Solution Approach 1:
The patent segments the high-frequency clock signal into lower-frequency divided clock signals for specific synchronization operations. By using these lower-frequency signals for command synchronization, the toggling operations are reduced, thereby decreasing power consumption while maintaining high operating speed for data operations using the original high-frequency external clock signal.
3Speed
If the external clock signal frequency is increased to improve operating speed, then the operating speed of the integrated circuit is improved, but the command recognition accuracy deteriorates
Solution Approach 1:
The patent divides the external clock signal into lower-frequency divided clock signals that are specifically used by the command generation circuit for synchronizing and recognizing external command signals. This segmentation ensures that command recognition operations are performed with sufficient timing margins and accuracy, while the main data processing operations can proceed at the higher external clock frequency.
Data Source
AI summary
An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.