Divided-Clock Phase Synchronization Circuit to Prevent False Lock
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Solution Overview
Problem
In electronic devices, divided clocks often fail to synchronize properly, leading to malfunctions and potential side effects when attempting to address this issue with existing solutions.
Innovation Solution
A method involving a synchronization control circuit with frequency dividers, phase relationship detection circuits, and logic gates to synchronize divided clocks, ensuring correct operation without inverting signals and avoiding false lock issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If divided clocks are generated independently in different circuits, then each circuit can operate autonomously, but the divided clocks may not be synchronized with each other causing malfunctions
Solution Approach 1:
The patent implements a feedback mechanism where the first synchronization control sub-circuit outputs both the first divided clock and a phase selection result signal to the second synchronization control sub-circuit. The second sub-circuit uses this feedback information along with phase relationship detection to determine whether to output the second divided clock or its inverted signal, ensuring synchronized operation while maintaining autonomous circuit design.
2Reliability
If phase relationship detection is performed to synchronize divided clocks, then clock synchronization is improved, but inversion errors and false lock issues may occur
Solution Approach 1:
The patent employs dynamic phase selection where the output of the second divided clock can be selectively inverted based on the phase relationship detection result. The second synchronization control sub-circuit dynamically adjusts its output by selecting between the non-inverted second divided clock and its inverted version, preventing inversion errors and false lock while maintaining synchronization.
3Reliability
If existing solutions are applied to address divided clock synchronization issues, then synchronization problems are attempted to be solved, but additional side effects are introduced
Solution Approach 1:
The patent segments the synchronization control function into independent synchronization control sub-circuits distributed in different circuits. Each sub-circuit independently performs frequency division and phase control, allowing localized synchronization management without introducing system-wide side effects. The first and second synchronization control sub-circuits operate semi-independently while maintaining coordination through signal exchange.
Data Source
AI summary
A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.