Clock Generator Feedback Path Using Divided Clocks for Lower Delay
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Solution Overview
Problem
Conventional clock generator circuits with feedback paths face issues of reduced responsiveness and increased power consumption due to the susceptibility of transistor circuitry to variations in operating and process conditions, leading to instability and decreased performance in clock signal generation.
Innovation Solution
The introduction of a feedback clock path that removes circuitry from the forward path while providing power savings and duty-cycle correction capabilities, utilizing a lower frequency clock signal for phase detection and duty-cycle correction, which reduces the overall gate count and propagation delay in the forward path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor circuitry is used in the forward clock path for duty-cycle correction and timing adjustment, then the clock signal can be conditioned and stabilized, but the propagation delay increases and responsiveness decreases
Solution Approach 1:
The patent segments the clock path into a forward path and a feedback path. The forward path contains only the delay lines (coarse and fine) without additional transistor circuitry, while the feedback path contains the DCC circuit and other conditioning circuits. This segmentation allows the forward path to remain fast and responsive while the feedback path provides stability and correction.
Solution Approach 2:
The patent extracts the DCC circuit and other timing adjustment circuits from the forward clock path and places them in the feedback path. This removal eliminates the propagation delay introduced by these circuits in the forward path, improving responsiveness while maintaining their stabilizing function through feedback.
2Reliability
If multiple correction circuits (DCC, tOH trim) are placed in the forward clock path, then comprehensive timing correction is achieved, but the gate count and power consumption increase
Solution Approach 1:
The patent segments the correction circuits into those placed in the feedback path (DCC circuit, tOH trim circuit) rather than the forward path. This reduces the gate count in the forward path, lowering power consumption while maintaining timing accuracy through feedback control.
Solution Approach 2:
The patent uses feedback mechanisms where the corrected clock signal from the feedback path is fed back to adjust the delay lines in the forward path. This allows comprehensive timing correction to be achieved through feedback control rather than through multiple series circuits in the forward path, reducing power consumption.
3Measurement precision
If the feedback path uses the full-frequency output clock signal, then phase detection accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent changes the frequency parameter of the clock signal used in the feedback path by using a divided version (lower frequency) instead of the full-frequency output clock signal. This parameter change reduces power consumption in the feedback path while phase detection accuracy is maintained through the use of appropriate phase detection techniques adapted to the divided frequency.
Data Source
AI summary
Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by an adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.