Divided Clock Circuit for Geardown Mode Timing Selection
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Solution Overview
Problem
Existing clock generation systems in electronic devices, such as DDR SDRAM memory devices, face challenges in efficiently generating divided clock signals that can adapt to different operational modes, like normal and geardown modes, with varying frequencies and cycle times, which affects the performance and power management.
Innovation Solution
A divided clock generation device and method that includes a chip selection flip-flop, clock division unit, clock comparator, and clock multiplexer to generate and select second divided clock signals based on a first divided clock signal, allowing for synchronization with specific edges and frequency reduction, enabling efficient operation in different modes by adjusting the internal clock signal's frequency and cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal clock signal frequency is reduced in geardown mode, then power consumption is reduced, but the operational speed decreases
Solution Approach 1:
The clock generation device dynamically adjusts the internal clock signal frequency based on operational mode. In geardown mode, the system selectively generates a divided clock signal with half the frequency of the first divided clock signal, allowing the device to operate at lower speeds when full performance is not required, thereby reducing power consumption while maintaining the ability to switch to higher frequencies when needed.
2Measurement precision
If the clock division unit generates second divided clock signals synchronized with falling edge, then timing precision is improved, but the circuit complexity increases
Solution Approach 1:
The clock division unit uses the falling edge of the first divided clock bar signal (a complementary signal) as an intermediary reference to generate the second divided clock signals. This intermediary approach allows precise synchronization without requiring complex timing circuits, as the falling edge provides a clear, well-defined timing reference point that simplifies the overall circuit design while maintaining high timing precision.
3Adaptability or versatility
If the clock comparator selects from multiple second divided clock signals, then adaptability to different modes is improved, but the control complexity increases
Solution Approach 1:
The clock comparator dynamically selects between multiple second divided clock signals (even and odd) based on the current operational mode and timing requirements. This dynamic selection capability allows the device to adapt to different modes (normal and geardown) without requiring separate clock generation circuits for each mode, thereby achieving versatility while keeping the control logic relatively simple through selective signal switching.
Data Source
AI summary
A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.