Divided Clock Gating for Lower-Power Memory Command Timing
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Solution Overview
Problem
Memory devices face increased power consumption due to the need to operate both even and odd circuitries simultaneously when processing commands, as the arrival of commands on even or odd edges of a global clock is unpredictable, leading to unnecessary activation of both divided clock and circuitry.
Innovation Solution
Implementing control logic to selectively enable and disable unused divided clock and circuitry based on the edge of the global clock where the command is received, ensuring only the necessary circuitry is activated for command processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both even and odd circuitries are operated simultaneously to handle unpredictable command arrivals, then command processing reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the operational state of divided circuitries based on real-time command arrival patterns. Control logic monitors which divided circuitry (even or odd) received the most recent command and selectively activates only that circuitry, transitioning the system from a static full-power mode to a dynamic adaptive mode that matches actual workload requirements.
Solution Approach 2:
The memory device divides its command processing circuitry into separate even and odd domains, each capable of independent operation. This localization allows the system to activate only the specific local circuitry needed for the current command, rather than forcing all circuitries to operate at full capacity, thereby reducing unnecessary power consumption while maintaining processing reliability.
2Productivity
If divided clock signals are generated for both even and odd edges, then command processing capability is improved, but device complexity increases
Solution Approach 1:
The control logic unit serves multiple functions: it monitors command arrivals on both even and odd clock edges, determines which divided circuitry should be active, generates appropriate enable signals, and coordinates the switching between even and odd domains. This multi-functional approach consolidates what could be separate complex control mechanisms into a single versatile unit, managing device complexity while maintaining high command processing capability.
3Use of energy by moving object
If control logic is added to selectively enable/disable circuitry, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the control logic functions with the existing command decoding and timing infrastructure. The control logic is integrated into the command receive chain, sharing resources with the decoder and timing units. This consolidation approach reduces the need for separate dedicated control circuits, thereby achieving power management capabilities without proportionally increasing overall device complexity.
Data Source
AI summary
Methods, systems, and devices for divided clock control are described. An even clock signal associated with transitioning edges of even-indexed pulses of a global clock signal and an odd clock signal associated with transitioning edges of odd-indexed pulses of a global clock signal may be received. An indication of whether a received command was received on a transitioning edge of an even-indexed pulse may be received. Based on the indication, whether to enable a propagation of the even clock signal to a first delay logic associated with even-indexed pulses or a second delay logic associated with odd-indexed pulses may be determined. Based on the determining, whether to delay a propagation of the command using the first delay logic and the even clock signal or the second delay logic and the odd clock signal may be determined.