Divided Clock Alignment Using Leaf-Triggered Pattern Selection

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Solution Overview

Problem

Clock frequency division in integrated circuits often results in desynchronization with external clock references, leading to synchronization issues at remote nodes of the network.

Innovation Solution

A method and circuitry that generate a clock signal by detecting a reference event at a leaf node, generating a synchronizing signal, and passing it through clocked storage cells to the root node, where a second clock is synchronized to account for propagation delay, ensuring alignment with the external clock reference even after frequency division.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If clock frequency division is performed to reduce clocking rate and power consumption, then power consumption is reduced, but synchronization with external clock reference is lost

Engineering Contradiction:
Improvepower consumptionVSAvoidsynchronization with external clock reference
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

A synchronizing signal is generated in advance at the leaf node based on the external reference clock, and this signal is propagated through the clock distribution network to the root node before clock division occurs. The root node uses this pre-propagated synchronizing signal to align the divided clock phases, ensuring that even though the clock frequency is reduced, the synchronization with the external reference is maintained through the preliminary establishment of timing relationships.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system establishes a feedback mechanism where the synchronizing signal generated at the leaf node (based on external reference) is propagated back to the root node, and the root node adjusts its divided clock output based on this feedback signal. This closed-loop feedback ensures that the power-saving clock division operation does not compromise synchronization, as the root node continuously aligns its output with the external reference through the feedback path.

Inventive Principle:
Principle #23Feedback

2Reliability

If clock is distributed over a network with significant delay, then synchronization at remote nodes is achieved, but propagation delay increases

Engineering Contradiction:
Improvesynchronization at remote nodesVSAvoidpropagation delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of the conventional approach where the root node generates the clock and distributes it to leaves (forward propagation), this invention inverts the synchronization signal flow: the leaf node generates the synchronizing signal based on the external reference and propagates it back to the root node (backward propagation). This inversion allows the system to compensate for propagation delays by establishing synchronization from the remote end, where the external reference is directly available, thereby reducing the effective synchronization delay despite the physical network delays.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS20160142067A1Frequency division clock alignment using pattern selection
Publication Date: 2016.05.19 MARVELL ASIA PTE LTD
  • US20160142067A1 patent drawing
  • US20160142067A1 patent drawing
  • US20160142067A1 patent drawing

AI summary

Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal.