Divided-Clock Phase Detection for Low-Power Signal Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become faster, synchronizing signals effectively while minimizing power consumption and reducing the need for large clock buffers remains a challenge, particularly in restoring full clock signals from divided clock signals.
Innovation Solution
A semiconductor device incorporating a divider circuit to generate divided clocks with a 90° phase difference and a detection circuit to produce phase and timing information signals based on control signals, data determination signals, and divided clocks, enabling precise synchronization and phase comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock chopper circuit is used to restore full clock signal from divided clock signals, then signal synchronization is achieved, but power consumption increases and large clock buffers are required
Solution Approach 1:
The patent extracts only the essential function of phase detection from the traditional clock chopper circuit. Instead of restoring the full clock signal, it detects phase information directly from divided clock signals using simple logic circuits, eliminating the need for large clock buffers and reducing power consumption while maintaining synchronization capability
Solution Approach 2:
The invention replaces expensive, power-intensive clock buffer circuits with simple, low-power logic circuits that perform phase detection. The solution uses basic logic gates and flip-flops instead of complex clock restoration circuitry, achieving the same synchronization function with minimal resources
2Reliability
If a clock chopper circuit is used to restore full clock signal, then signal synchronization is achieved, but device size increases due to large clock buffers
Solution Approach 1:
The patent extracts only the essential function of phase detection from the traditional clock chopper circuit. Instead of restoring the full clock signal, it detects phase information directly from divided clock signals using simple logic circuits, eliminating the need for large clock buffers and reducing power consumption while maintaining synchronization capability
Solution Approach 2:
The invention replaces expensive, power-intensive clock buffer circuits with simple, low-power logic circuits that perform phase detection. The solution uses basic logic gates and flip-flops instead of complex clock restoration circuitry, achieving the same synchronization function with minimal resources
3Use of energy by moving object
If divided clock signals are used instead of full clock signal, then power consumption is reduced, but signal synchronization becomes difficult
Solution Approach 1:
The patent introduces phase detection signals as an intermediary that bridges divided clock signals and synchronization requirements. By detecting phase relationships between divided clocks and data signals, the system achieves synchronization without needing to restore full-speed clock signals, maintaining low power consumption while ensuring proper timing alignment
Data Source
AI summary
A semiconductor device may include a divider circuit and a detection circuit. The divider circuit may divide an external clock to generate a plurality of divided clocks. The detection circuit may generate a phase information signal and a timing information signal based on a plurality of data determination signals and the plurality of divided clocks.