Divided Clock Distribution Using Register-Based Synchronization
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Solution Overview
Problem
Existing clock signal distribution networks are resource intensive and face challenges in synchronizing clock signals across a chip, especially when distributing two different-speed clock signals, with delay-compensated networks being affected by PVT variations.
Innovation Solution
A clock signal network that uses a series of registers clocked by a full-speed clock signal to distribute and synchronize a divided clock signal, allowing both full-speed and divided clock signals to be distributed to IO and core circuitry, with flexibility in configuring registers as either divided clock sources or distribution registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay-compensated networks are used to distribute clock signals, then different length distribution lines can be used, but the amount of delay imparted by individual delay elements is affected by PVT variations making it difficult to achieve wide distribution of a synchronized clock signal
Solution Approach 1:
A buffer register is introduced as an intermediary element in the clock distribution network. The buffer register receives the clock signal from a first distribution line and transfers it to a second distribution line, acting as a synchronization mediator. This intermediary buffer ensures that clock signals arriving at different times due to varying path lengths are resynchronized, eliminating the sensitivity to PVT variations that affects delay elements in traditional delay-compensated networks.
Solution Approach 2:
The buffer register automatically adjusts the timing of clock signals based on their arrival times at different distribution points. By using the buffer register's inherent storage capability, the system self-corrects for path length differences without requiring external calibration or adjustment mechanisms, making the network inherently resilient to PVT variations.
2Reliability
If equal-branch-length clock trees are used to distribute clock signals, then the clock signal is substantially synchronized across distribution points, but additional clock networks are required to distribute different-speed clock signals
Solution Approach 1:
The buffer register serves multiple functions within a single clock distribution network: it acts as both a signal transfer element and a synchronization mechanism for different-speed clock signals. By making the buffer register configurable and multi-functional, the patent eliminates the need for separate clock networks for different speeds, as the same network infrastructure can handle multiple clock frequencies through the versatile buffer register elements.
Solution Approach 2:
The clock distribution network is segmented into multiple distribution lines with buffer registers at strategic points. This segmentation allows the network to be divided into manageable sections, each capable of handling different clock speeds independently, while maintaining overall synchronization through the coordinated operation of buffer registers throughout the segmented network.
3Reliability
If delay elements are added to shorter length routes in delay-compensated networks, then propagation delay at different distribution points can be equalized, but the network becomes more resource intensive
Solution Approach 1:
The patent uses buffer registers, which are simpler and more readily available standard circuit elements,替代complex delay elements. Buffer registers are essentially flip-flops with buffering capability, making them cheaper and more abundant in standard cell libraries. By using these simpler elements instead of specialized delay elements, the patent reduces resource intensity while achieving the same delay equalization function.
Data Source
AI summary
Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.