Divided CMOS Image Sensor Bit Lines for Frame Rate
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Solution Overview
Problem
The frame rate of image sensors is limited by the bit line settling time, which can be improved by reducing bit line capacitance, currently achieved through dividing bit lines into separate portions that are electrically isolated from each other.
Innovation Solution
Dividing column bit lines into 'top' and 'bottom' portions near the middle, with each portion being coupled to a single readout circuit through hybrid bonds, reducing capacitance and settling time, thereby enhancing the frame rate of CMOS image sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit lines are divided into separate portions that are electrically isolated from each other, then bit line capacitance is reduced and frame rate is improved, but device complexity increases due to additional isolation structures and readout circuit connections
Solution Approach 1:
The bit lines are divided into multiple separate portions along their length, with electrically isolating structures positioned between adjacent portions. Each portion is independently connected to readout circuits, enabling parallel operation and reducing the capacitance of each individual bit line segment, thereby improving frame rate.
Solution Approach 2:
Electrically isolating structures are introduced as intermediary elements between adjacent bit line portions. These isolating structures act as mediators that prevent electrical coupling between portions while maintaining physical proximity for compact layout, thus reducing capacitance without excessive complexity.
2Loss of time
If bit line segments are shortened through division, then settling time is reduced and frame rate increases, but manufacturing precision requirements increase due to precise positioning of isolating structures
Solution Approach 1:
By segmenting bit lines into shorter portions with isolating structures positioned at specific locations, the effective length of each bit line segment is reduced. This segmentation directly reduces the time required for signal settling while the standardized positioning of isolating structures helps manage manufacturing precision requirements.
Solution Approach 2:
The electrically isolating structures are designed and positioned in advance during the layout phase, establishing predetermined segmentation points that optimize bit line length for settling time requirements while accounting for manufacturing capabilities.
3Productivity
If bit lines are divided and connected to single readout circuits through hybrid bonds, then capacitance is reduced and frame rate is enhanced, but ease of manufacture decreases due to hybrid bonding process complexity
Solution Approach 1:
Bit lines are segmented into portions that are independently bonded to readout circuits using hybrid bonding technology. This segmentation enables reduced capacitance per segment and improved frame rate, while the modular approach allows for systematic integration processes.
Solution Approach 2:
Hybrid bonds serve as intermediary connection structures between the divided bit line portions and readout circuits. These bonds enable electrical connection while maintaining physical separation, facilitating the segmented architecture that improves performance despite added manufacturing steps.
Data Source
AI summary
An image sensor includes a pixel array including a plurality of pixels. A bit line is coupled to a column of pixels of the pixel array. The bit line is separated in to a plurality of portions coupled to the column of pixels. The portions of the bit line are electrically isolated from one another. A readout circuit is coupled to a first portion of the bit line coupled to a first portion of rows of pixels from the column of pixels to read image data from the first portion of rows of pixels from the column of pixels. The readout circuit is further coupled to a second portion of the bit line coupled to a second portion of rows of pixels from the column of pixels to read image data from the second portion of rows of pixels from the column of pixels.