Divided DQS Clock Capture for High-Speed Memory Timing Alignment
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Solution Overview
Problem
In semiconductor memory, achieving proper timing of internal command and clock signals is challenging due to high clock frequencies and varying latency, which can result in incorrect or incomplete data capture, especially in multi-data rate memories where data rates exceed clock frequencies and timing domains need to be crossed.
Innovation Solution
The apparatus includes a clock divider to provide divided DQS signals, a setup and hold circuit, and a deserialize circuit to capture and sort data based on flag signals, ensuring accurate data capture by aligning the DQS signal edges with the command signal timing, even with varying preamble lengths and propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve data transmission rate, then productivity is improved, but the timing precision deteriorates making it difficult to capture data correctly
Solution Approach 1:
The patent divides the high-frequency clock signal into multiple lower-frequency divided clock signals using a clock divider circuit. This segmentation allows data capture circuitry to operate at lower frequencies where timing is more manageable, while still supporting high-speed data transmission through coordinated use of multiple divided clock phases.
Solution Approach 2:
The patent introduces divided clock signals as an intermediary between the high-frequency external clock and the data capture operations. These divided clocks act as mediators that bridge the timing domain gap, enabling accurate data sampling without requiring the capture circuitry to directly handle the full clock frequency.
2Manufacturing precision
If delay circuitry is added to align DQS and command timing, then timing alignment is improved, but propagation delay variations worsen due to process, voltage, and temperature conditions
Solution Approach 1:
The patent uses dynamically adjustable delay circuitry that can adapt to varying process, voltage, and temperature conditions. The delay elements are designed to be tunable, allowing the system to optimize timing alignment under different operating conditions rather than relying on fixed delay values that may drift.
Solution Approach 2:
The patent changes the delay parameters of internal circuit paths to achieve proper timing alignment. By adjusting delay parameters dynamically and using divided clock signals with different phases, the system can compensate for PVT variations without adding excessive static delay circuitry.
3Adaptability or versatility
If the preamble length is varied to accommodate different stabilization requirements, then adaptability is improved, but the reliability of DQS timing reference deteriorates
Solution Approach 1:
The patent uses the preamble period to perform preliminary actions of stabilizing the DQS signal and initializing data capture circuitry before actual data transmission begins. This preliminary stabilization phase ensures that when data capture starts, the timing reference is reliable regardless of the eventual data rate or mode of operation.
Solution Approach 2:
The patent designs the DQS signal to serve multiple functions: it acts as both a data sampling clock and a timing reference for command synchronization. The universal DQS signal maintains its timing reference reliability across different operating modes by using the divided clock generation approach that works consistently whether the preamble is short or long.
4Ease of operation
If tDQSS variation range is increased to accommodate clock edge alignment options, then ease of operation is improved, but timing precision deteriorates
Solution Approach 1:
The patent segments the clock cycle into multiple phases using the divided clock signals, each with specific phase relationships to the DQS signal. This segmentation allows the system to select appropriate phase alignments for different operating conditions while maintaining precise timing control through the structured phase distribution.
Solution Approach 2:
The patent employs timing detection circuitry that monitors the actual timing relationship between DQS edges and data arrivals, providing feedback to adjust the divided clock phase alignment. This feedback mechanism ensures that even with variable tDQSS settings, the system maintains accurate timing by dynamically compensating for deviations.
Data Source
AI summary
Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.