Divided Gate Electrode for Thin Film Transistor Substrates
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Solution Overview
Problem
The existing gray tone exposure method for manufacturing inverted staggered type thin film transistor substrates faces challenges in achieving uniform resist film thickness, leading to incomplete etching and potential short circuits due to variations in gate wiring patterns, which complicates the formation of uniform back channel portions and increases manufacturing costs.
Innovation Solution
The solution involves dividing the gate wiring into multiple parallel patterns, allowing for controlled resist film thickness uniformity through gray tone exposure, ensuring stable etching and ashing processes by maintaining a specific ratio of wiring width to space, thereby improving yield and preventing disconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gray tone exposure is applied to back channel portion of TFT to reduce manufacturing steps, then productivity is improved, but resist film thickness becomes non-uniform due to gate wiring pattern variations
Solution Approach 1:
The gate wiring is designed with different local widths: a first width in the pixel region and a second width (greater than the first) in the non-pixel region. This local variation compensates for the shadow effect during gray tone exposure, ensuring uniform resist film thickness across the entire substrate while maintaining the productivity benefits of the simplified manufacturing process.
2Adaptability or versatility
If gate wiring width is increased in non-pixel regions for test circuits or additional functions, then adaptability is improved, but resist film thickness uniformity deteriorates
Solution Approach 1:
The gate wiring width is locally adjusted: wider in non-pixel regions to accommodate test circuits or additional functions, and narrower in pixel regions. This local quality variation ensures that despite the width difference, the resist film thickness remains uniform across the entire substrate after gray tone exposure, resolving the contradiction between adaptability and manufacturing precision.
3Reliability
If resist film thickness varies due to gate wiring pattern, then etching completeness becomes unreliable, but manufacturing cost increases if process complexity is increased to compensate
Solution Approach 1:
Instead of increasing process complexity (such as multiple exposure steps or additional process controls), the gate wiring structure itself is modified with local width variations. This structural adjustment passively ensures uniform resist film thickness and reliable etching completeness, maintaining simplicity while improving reliability.
4Manufacturing precision
If multiple exposure processes are used to achieve uniform resist thickness, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The gate wiring is designed with pre-calculated local width variations that optically compensate for the shadow effect during gray tone exposure. This allows a single exposure process to achieve uniform resist film thickness, eliminating the need for multiple exposure processes and maintaining high productivity while ensuring manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform resist film thickness across different gate wiring regions, enabling stable etching and ashing processes, reducing manufacturing costs, and enhancing the reliability of thin film transistor substrates by preventing short circuits and disconnections.
Implementation Method 1
a back channel portion of the thin film transistor is removed by gray tone exposure in a region where the source wiring and the drain wiring intersect with each other
Data Source
AI summary
In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.