Divided Multi-Connector PCI Express Bus for High-Bandwidth Graphics
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Solution Overview
Problem
Current connectors for electronic devices, particularly those using PCI Express™ interfaces, are too large and costly, limiting their suitability for smaller devices due to size and heat dissipation constraints, and often only support single-lane communication, which is insufficient for high-bandwidth graphics processing.
Innovation Solution
A compact, 16-lane PCI Express™ compatible connector with a divided multi-connector element differential bus design, featuring a housing with a footprint of approximately 12 mm×53 mm and 124 pins, divided into two 8-lane groups with mirrored contact configurations, allowing for high-speed multilane communication while reducing the physical size and pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a 16-lane PCI Express connector is used to provide high bandwidth for graphics processing, then communication performance is improved, but connector size and footprint become too large for consumer devices
Solution Approach 1:
The connector is divided into two separate 8-lane connector elements housed within a single housing. Each connector element independently provides 8 lanes of PCI Express communication, allowing the system to achieve 16-lane total bandwidth while using compact, standardized 8-lane connector footprints that are suitable for consumer devices.
2Productivity
If more pins are added to support 16 lanes of communication, then data transmission capability is improved, but manufacturing cost and complexity increase
Solution Approach 1:
Instead of manufacturing a single complex 16-lane connector with numerous pins, the design segments the connection into two independent 8-lane connector elements. Each element uses a standardized pin configuration that is simpler to manufacture, while together they provide the required 16-lane data transmission capability.
3Productivity
If graphics processing power is increased to meet multimedia demands, then processing performance is improved, but heat dissipation requirements exceed device limits
Solution Approach 1:
The patent introduces an external graphics processing device that acts as an intermediary, handling intensive graphics processing tasks outside the mobile device. The compact 16-lane connector enables high-speed communication between the mobile device and external graphics processor, allowing the mobile device to offload heat-generating processing while maintaining high graphics performance.
Data Source
AI summary
A method includes reducing power of a first graphics processor by disabling or not using its rendering engine and leaving a display engine of the same first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display. A display frame is rendered by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state, such as a non-rendering state. The rendered frame is stored in a corresponding second frame buffer of the second graphics processor, such as a local frame buffer and copied from the second frame buffer to the first frame buffer. The copied frame in the first frame buffer is then displayed on a display while the rendering engine of the first graphics processor is in the reduced power state. Accordingly thermal output and power output is reduced with respect to the first graphics processor since it does not do frame generation using its rendering engine, it only uses its display engine to display frames generated by the second graphics processor.