Divided Source Plate for Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high capacity and integration while maintaining excellent electrical characteristics, particularly due to electrical interference between the source plate and logic structure, which can lead to malfunctions in the slimming region vulnerable to interference.
Innovation Solution
The semiconductor memory device incorporates a substrate with a cell region and a slimming region, where the source plate is divided by a first slit at the boundary between the two regions, with the second source plate in the slimming region being electrically isolated from the first source plate in the cell region, reducing electrical interference and allowing the second source plate to float regardless of device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the source plate is made as a single continuous structure to simplify device structure, then device complexity is reduced, but electrical interference occurs between the source plate and logic structure in the slimming region
Solution Approach 1:
The source plate is divided into multiple separate source plates (first source plate in cell region, second source plate in slimming region) by introducing a first slit. This segmentation isolates the source plates in different regions, preventing electrical interference between the source plate and logic structure in the slimming region while maintaining simplified individual structures.
2Ease of operation
If the source plate in the slimming region is electrically connected to the logic structure to enable normal operation, then operational functionality is maintained, but electrical interference causes malfunctions
Solution Approach 1:
By dividing the source plate into separate regions with a first slit, the patent enables the second source plate in the slimming region to be electrically isolated from the logic structure. This prevents electrical interference while the source plate in the cell region remains connected for normal operation, thus maintaining functionality while improving reliability.
Solution Approach 2:
The patent applies different electrical connection configurations to different regions: the first source plate in the cell region is electrically connected to support normal operation, while the second source plate in the slimming region is electrically isolated to prevent interference. This local differentiation resolves the contradiction between operational functionality and reliability.
3Reliability
If the source plate is divided into separate regions to reduce electrical interference, then electrical characteristics are improved, but device structure becomes more complex
Solution Approach 1:
The source plate is segmented into separate regions using a first slit, which improves electrical characteristics by preventing interference. The segmentation is implemented in a straightforward manner that divides the source plate into manageable sections without introducing excessive structural complexity.
Solution Approach 2:
The first slit acts as an intermediary element that divides the source plate into separate regions. This simple intermediary structure effectively reduces electrical interference while adding minimal complexity to the overall device architecture.
Data Source
AI summary
A semiconductor memory device includes a substrate including a cell region and a slimming region; a logic structure disposed over the substrate, the logic structure including logic circuit elements and bottom wiring lines electrically coupled to the logic circuit elements; a source plate disposed over the logic structure; a memory structure including a plurality of memory cells and a plurality of gate electrode layers, wherein the plurality of memory cells are disposed over the source plate of the cell region and a plurality of gate electrode layers are stacked over the source plate of the cell region and the slimming region to be separated from one another and are coupled to the plurality of memory cells; and a first slit cutting the source plate at a boundary between the cell region and the slimming region, wherein the source plate of the slimming region is floated regardless an operation of the memory cells and the logic circuit elements.