Divided Vertical Signal Lines for High-Speed Image Capture
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Solution Overview
Problem
Conventional solid-state image capturing devices face challenges in capturing high-quality monitor images at high speed due to increased load on readout lines and signal mixing, which leads to moire occurrence and reduced image quality.
Innovation Solution
The device employs a configuration where vertical signal lines are divided into two parts between the upper and lower regions of the pixel portion, with different division positions for each line, allowing pixel signals to be read out through multiple vertical signal lines, reducing readout time and suppressing moire occurrence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the area of the pixel portion is increased to enhance resolution and image quality, then the number of pixels and quantity of light input are increased, but the load on readout lines increases and readout time becomes longer
Solution Approach 1:
The pixel portion is divided into upper and lower regions, with different vertical signal lines extending from each region. This segmentation allows parallel readout of signals from both regions, reducing the overall readout time while maintaining high pixel counts for high-quality imaging
2Speed
If vertical signal lines are divided at the same position to accelerate readout, then readout speed is enhanced, but moire occurs in captured images
Solution Approach 1:
The vertical signal lines are divided at different positions in the row direction for different columns. This asymmetric division pattern prevents the formation of regular interference patterns (moire) while still achieving accelerated readout through parallel signal processing paths
3Productivity
If multiple vertical signal lines are used to read out pixel signals simultaneously, then readout time is reduced, but the complexity of the readout circuit increases
Solution Approach 1:
The pixel portion is segmented into upper and lower regions with distinct vertical signal line groups, allowing simultaneous readout through multiple lines while maintaining organized, manageable circuit architecture
Solution Approach 2:
Different columns have different division positions for their vertical signal lines, optimizing the local readout configuration for each column while maintaining overall system efficiency and preventing moire patterns
Data Source
AI summary
In a solid-state image capturing device, one or more vertical signal lines are disposed along one of columns of a pixel portion, and each of the vertical signal lines is divided into two parts between an upper region and a lower region of the pixel portion. Pixel signals output from a plurality of pixels of the one of the columns are read out to a plurality of column readout circuits through two or more parts of the vertical signal lines including the two parts of the one or more vertical signal lines disposed along the one of the columns. A division position of one vertical signal line among the vertical signal lines disposed in the pixel portion is different from a division position of another vertical signal line among the vertical signal lines in a row direction.