Multi-Modulus Divider Chain Control Without Intermediate Divisors
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Solution Overview
Problem
Existing multi-modulus divider circuits for clock generation in phase-locked loop integrated circuits face issues with intermediate divisors when changing the divisor value, leading to errors in fractional division ratios.
Innovation Solution
A cascaded chain of div2/3 cells with chain length control operation that prevents the generation of intermediate divisors by turning off non-participating cells and using a Boolean combination of bits from the chain length control byte to control active stages, ensuring a valid update time interval for divisor changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-modulus divider changes divisor value dynamically, then frequency adaptability is improved, but intermediate divisors are generated causing division ratio errors
Solution Approach 1:
The patent applies preliminary action by establishing a valid update time interval before allowing divisor value changes. The divisor update is permitted only when all modulus input signals are at a first logic state (e.g., all low), ensuring the change occurs at a predetermined safe moment when no intermediate divisor can be generated. This preliminary condition check prevents division ratio errors while maintaining frequency adaptability.
2Speed
If all div2/3 cells remain active during operation, then response speed is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the activity state of div2/3 cells variable rather than static. Cells are dynamically switched between active and inactive states based on their participation in the current division operation. The chain length control byte determines which cells are active, allowing the system to adapt power consumption to the actual operational needs while maintaining fast response when cells are active.
Solution Approach 2:
The patent applies discarding and recovering by temporarily deactivating (discarding) non-participating div2/3 cells to save power, and reactivating (recovering) them when needed. The inactive cells are kept in a ready state with their modulus input terminals properly configured, allowing rapid reactivation without full initialization, thus balancing power savings with response speed.
3Adaptability or versatility
If chain length control updates divisor value, then frequency tuning range is improved, but intermediate divisor states occur causing errors
Solution Approach 1:
The patent applies feedback by monitoring the states of all modulus input signals to determine whether a valid update time interval exists. The chain length control operation is enabled only when feedback indicates all modulus inputs are at the required logic state, creating a self-regulating mechanism that prevents intermediate divisor states while allowing full frequency tuning range.
Data Source
AI summary
Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P<n:0> during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.