Frequency Divider Delay Tuning for Quadrature Error Correction
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Solution Overview
Problem
IQ imbalance in transceivers due to mismatches between in-phase and quadrature signal paths limits performance, requiring effective quadrature error correction to improve signal integrity for high-speed transmitters and receivers.
Innovation Solution
A frequency divider circuit with a master and slave latch configuration, including current supplying circuits and a current steering circuit, that introduces variable delays to correct quadrature errors by adjusting load resistances and clock signals, allowing individual turnability for phase correction without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional frequency divider circuits are used without quadrature error correction, then the circuit complexity remains low, but signal integrity and quadrature accuracy deteriorate due to IQ imbalance
Solution Approach 1:
The patent merges the quadrature error correction function with the frequency divider circuit by integrating delay elements directly into the latch structure. The master and slave latches incorporate delay paths that correct quadrature errors while simultaneously performing frequency division, eliminating the need for separate correction circuits and maintaining low complexity while improving signal integrity.
Solution Approach 2:
The frequency divider circuit is designed to perform multiple functions: frequency division and quadrature error correction. The same latch circuitry that divides the clock frequency also contains adjustable delay elements that compensate for IQ imbalance, making the circuit universal and avoiding additional dedicated correction hardware.
2Reliability
If additional correction circuitry is added to correct quadrature errors, then signal integrity improves, but device complexity and area increase
Solution Approach 1:
The correction functionality is merged into the existing frequency divider latch circuitry. Delay elements are integrated within the master and slave latch structures rather than being added as separate external circuits, thus correcting quadrature errors without increasing overall device complexity or occupying additional area.
Solution Approach 2:
The frequency divider circuit performs self-correction of quadrature errors through integrated delay elements that are part of its internal structure. The circuit serves its own correction needs without requiring external correction hardware, reducing overall system complexity while maintaining signal integrity.
3Reliability
If delay elements are integrated into the frequency divider, then quadrature error correction is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The delay elements are implemented locally within each latch structure using the same physical layout and process parameters. By placing delay elements in identical locations within the master and slave latches, the patent ensures local matching of delay characteristics, reducing the impact of manufacturing variations and minimizing the need for high-precision manufacturing.
Solution Approach 2:
The patent uses homogeneous structures for the delay elements, employing identical circuit topologies and physical implementations in both the master and slave latches. This homogeneity ensures that delay characteristics match closely despite manufacturing variations, achieving quadrature error correction without requiring excessive manufacturing precision.
Data Source
AI summary
The present disclosure relates to a method for quadrature error correction using a frequency divider circuit. The method comprises delaying input of data to master input terminals and/or slave input terminals of the frequency divider circuit for correcting a quadrature error between the in-phase and quadrature-phase output signals.