Dividerless PLL Lock Control Using an Adaptive Phase Detector
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Solution Overview
Problem
Existing phase-locked loop (PLL) architectures, particularly fractional-N PLLs, face challenges in achieving high performance while minimizing power consumption and complexity, as the feedback divider consumes significant power due to its high speed and complexity.
Innovation Solution
The proposed PLL architecture employs a course fractional-N or integer divider for initial lock, which is then turned off, with an adaptive phase detector taking over to maintain frequency lock, using a digital delta sigma modulator to generate control signals and monitor frequency stability, allowing the PLL to operate without a feedback divider in a low power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a feedback divider is used in fractional-N PLL architecture, then frequency multiplication and lock capability are achieved, but power consumption increases significantly
Solution Approach 1:
The patent extracts the feedback divider from the active PLL loop after initial lock is achieved. The system uses a coarse fractional-N or integer divider for initial frequency acquisition and lock detection, then removes this divider from the signal path to eliminate its power consumption during normal operation, while maintaining frequency multiplication through the VCO and APD
2Use of energy by moving object
If feedback divider is disabled to save power, then power consumption decreases, but frequency lock monitoring capability is lost
Solution Approach 1:
The system implements self-service through the adaptive phase detector that continuously monitors the phase relationship between the reference clock and VCO output. The APD automatically detects frequency lock conditions and maintains system stability without requiring the feedback divider, effectively making the system monitor its own lock status through the inherent phase detection function
Solution Approach 2:
The patent implements feedback through the adaptive phase detector that continuously compares the VCO output phase with the reference clock phase. This feedback mechanism provides real-time lock detection and automatic correction, replacing the traditional feedback divider's monitoring function while enabling the divider to be disabled for power savings
Data Source
AI summary
A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.