Divider-Less PLL Feedback Using Delay-Gated Clock Sampling
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Solution Overview
Problem
Phase locked loops (PLLs) face high power consumption due to the presence of dividers, which is undesirable in many applications.
Innovation Solution
A divider-less PLL design that includes a phase frequency detector, charge pump, voltage controlled oscillator, delay unit, and clock gating unit, where the clock gating unit samples the output signal to generate a feedback signal, eliminating the need for a divider and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a divider is used in the PLL to perform phase tracking and frequency division, then the phase tracking functionality is achieved, but the power consumption increases significantly
Solution Approach 1:
The patent removes the divider component from the traditional PLL architecture entirely. Instead of using a divider to perform frequency division and phase tracking, the invention extracts only the essential phase detection functionality needed for PLL operation, eliminating the power-consuming divider while maintaining core functionality through alternative means.
Solution Approach 2:
The patent replaces the mechanical/divider-based frequency division system with an all-digital signal processing approach. The clock gating unit and delay unit work together to achieve frequency division through digital logic operations rather than traditional divider circuits, significantly reducing power consumption while maintaining the same functional outcome.
2Use of energy by moving object
If a divider is removed from the PLL to reduce power consumption, then the power consumption decreases, but the ability to perform frequency division and phase tracking may be compromised
Solution Approach 1:
The patent introduces a delay unit as an intermediary component between the VCO and the clock gating unit. This delay unit generates a delayed version of the reference signal that serves as a gating signal, enabling the clock gating unit to perform frequency division and phase tracking functions without requiring a traditional divider. The delay unit acts as a mediator that facilitates the alternative frequency division mechanism.
Solution Approach 2:
The clock gating unit performs multiple functions simultaneously - it gates the VCO output based on the delayed reference signal, performs frequency division, and generates the feedback signal for phase comparison. This self-service approach consolidates multiple divider-related functions into a single unit, eliminating the need for separate divider components while maintaining full frequency division capability.
Data Source
AI summary
A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.