Dividerless PLL Sampled Lowpass Filter for Low In-Band Noise
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Solution Overview
Problem
Existing phase-lock-loops (PLLs) face challenges in reducing in-band noise, power, and area overheads, particularly in deep sub-micron processes, due to inferior noise performance of ring oscillators and issues with pedestal and aperture errors in sub-sampling PLLs.
Innovation Solution
A dividerless PLL design incorporating a sampled lowpass filter structure with a phase detector, charge pump, and voltage-controlled oscillator, featuring a lowpass filter and sample-and-hold block, which uses a ripple rejection capacitor and current mirror configuration to mitigate noise and linearity issues, and eliminates the need for explicit frequency divider circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If sub-sampling phase-lock-loops (SSPLLs) are used to reduce in-band noise, then in-band noise performance is improved, but power and area overheads increase due to large sampling circuitry
Solution Approach 1:
The patent extracts the sampling operation from the traditional SSPLL architecture and implements it through a dividerless design with a sampled lowpass filter structure. By removing the explicit frequency divider and repositioning the sampling function within the loop filter, the design achieves noise reduction without the associated power and area penalties of large sampling circuitry.
Solution Approach 2:
The patent changes the sampling frequency parameter to be equal to the reference frequency, which is a significant departure from traditional SSPLL designs. This parameter change, combined with the dividerless architecture, enables the system to achieve the noise performance of SSPLLs with substantially reduced power consumption and circuit complexity.
2Object-generated harmful factors
If sub-sampling phase-lock-loops (SSPLLs) are used to reduce in-band noise, then in-band noise performance is improved, but area overheads increase due to large sampling circuitry
Solution Approach 1:
The patent extracts the sampling operation from the traditional SSPLL architecture and implements it through a dividerless design with a sampled lowpass filter structure. By removing the explicit frequency divider and repositioning the sampling function within the loop filter, the design achieves noise reduction without the associated power and area penalties of large sampling circuitry.
Solution Approach 2:
The patent uses a current mirror configuration to copy and replicate current signals, enabling the charge pump to provide accurate current modulation without requiring large sampling circuitry. This copying mechanism allows the system to achieve high precision with compact circuit implementation.
3Productivity
If traditional PLLs with frequency dividers are used, then frequency division is achieved, but phase-detector/charge-pump N2 noise dominates in-band noise
Solution Approach 1:
The patent extracts and removes the explicit frequency divider from the PLL core loop, creating a dividerless architecture. By taking out the divider, the system eliminates the source of N2 noise while maintaining frequency multiplication capability through the VCO and feedback path, achieving frequency division functionality without the associated noise penalty.
Solution Approach 2:
Instead of using a frequency divider to reduce frequency, the patent inverts the approach by using a dividerless design where the VCO operates at a frequency that is an integer multiple of the reference frequency. The frequency relationship is established through the feedback path rather than through division, effectively doing the opposite of traditional PLL design.
4Ease of operation
If charge pump provides analog range of currents in SSPLL, then loop control is achieved, but nonlinearity increases due to channel length modulation in deep sub-micron processes
Solution Approach 1:
The patent uses a current mirror configuration to copy reference currents and provide accurate current modulation in the charge pump. This copying mechanism ensures that the charge pump currents remain proportional to the control voltage across the full operating range, maintaining linearity even in deep sub-micron processes where channel length modulation would otherwise cause significant nonlinearity.
Solution Approach 2:
The patent changes the operating parameters of the charge pump by using a dividerless architecture with sampling at reference frequency. This parameter change allows the charge pump to operate in a regime where linearity is maintained through the current mirror configuration, avoiding the channel length modulation issues that plague traditional analog charge pumps in deep sub-micron technologies.
Data Source
AI summary
The present disclosure relates to a phase-lock-loop, which includes a phase detector (PD), a charge pump (CP), a sampled lowpass filter structure, and a voltage-controlled oscillator (VCO) structure. The PD is configured to receive a RF output signal from the VCO structure and a reference signal, and generate detection signals, which indicate a phase relationship between the RF output signal and the reference signal. The CP is configured to receive the detection signals and generate a CP current. Herein, the CP current flows into or out of the sampled lowpass filter structure based on the detection signals. The sampled lowpass filter is configured to provide an oscillator control voltage, which remains constant within a cycle of the reference signal, to the VCO structure based on the CP current. Based on the oscillator control voltage, the VCO structure is configured to tune the RF output signal.