Division Circuit Architecture Using Tree Structure for Partial Remainders
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Solution Overview
Problem
Conventional circuit architectures for division by constants in integrated circuits are slow and occupy a large silicon area, leading to higher power consumption and inefficiency, especially in graphics processing units (GPUs) where division operations are frequent.
Innovation Solution
A circuit architecture utilizing a tree structure to generate and combine partial remainders, allowing for parallel calculations and reducing the delay to O(log2N) and silicon area to O(Nlog2N), with additional optimizations such as bit shifting and zero-padding for division by even numbers and fast round-to-zero division of signed integers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional radix-2 non-restoring or radix-4 non-restoring division architectures are used, then the division functionality is achieved, but the delay is O(Nlog2N) and the area is O(N2 log2N)
Solution Approach 1:
The dividend is segmented into blocks of n bits, and the division is performed by calculating partial remainders for each block independently using a tree structure. This segmentation allows parallel processing and reduces the overall delay from O(Nlog2N) to O(log2N) while maintaining manageable complexity through modular block processing.
Solution Approach 2:
The patent transitions from sequential division operations to parallel operations by introducing a tree structure that processes multiple partial remainders simultaneously. This dimensional change from sequential to parallel processing reduces the critical path delay significantly while the area complexity is controlled by the O(Nlog2N) footprint achieved through efficient tree-based organization.
2Area of stationary object
If smaller architectures with area O(N2) are used, then the silicon area is reduced, but the delay increases to O(N2)
Solution Approach 1:
The dividend is divided into blocks of n bits, allowing parallel calculation of partial remainders. This segmentation enables the architecture to achieve both reduced area (O(Nlog2N)) and reduced delay (O(log2N)) by processing multiple segments simultaneously rather than sequentially.
Solution Approach 2:
Partial remainders are calculated in advance for each block of the dividend using the tree structure before final quotient generation. This preliminary calculation of partial remainders enables faster overall division by avoiding sequential processing and allowing parallel computation of remaining digits.
3Use of energy by stationary object
If conventional division architectures are used, then the division functionality is provided, but power consumption increases due to larger footprint
Solution Approach 1:
By segmenting the dividend into blocks and using a tree structure to process them in parallel, the architecture reduces the active circuit footprint from O(N2 log2N) to O(Nlog2N). This segmentation-based approach decreases the number of simultaneously active components, thereby reducing power consumption while maintaining division functionality.
Solution Approach 2:
The patent reorganizes the division architecture from a sequential one-dimensional processing model to a parallel multi-dimensional tree structure. This dimensional transformation reduces the critical path and active area, leading to lower power consumption while preserving the O(Nlog2N) area efficiency.
Data Source
AI summary
For a division of a dividend by a constant divider, a circuit architecture may calculate partial remainders. The circuit architecture may implement a tree structure to generate intermediate signals of partial remainders and combine adjacent intermediate signals to generate other partial remainders downstream. The circuit architecture may generate a quotient based on the partial remainders. The circuit architecture may also implement bit shifting and zero-padding on left side of the dividend to generate bit-level partial remainders. Furthermore, the circuit architecture may enable a fast round-to-zero division of signed integers by flipping the input bits of a negative integer and output bits of the corresponding quotient and performing only one increment operation, either before the division or after the division. In addition, the circuit architecture may also perform a division of a dividend in a carry-save form.