Division Clock Phase Calibration During Self-Refresh Blocking
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Solution Overview
Problem
Semiconductor devices experience phase flips in division clocks due to interruptions during self-refresh operations, leading to data input/output errors.
Innovation Solution
Incorporating a clock division circuit that stops generating division clocks during a block section when a block command is detected, along with a clock latch circuit to manage internal clocks and a block control pulse generating circuit to sequence control pulses, ensuring phase calibration of division clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock division circuit continuously generates division clocks during self-refresh operations, then the clock operation remains uninterrupted, but phase flips occur causing data input/output errors
Solution Approach 1:
The patent extracts the problematic continuous clock generation during self-refresh operations by introducing a block control mechanism. The block control pulse generating circuit detects self-refresh commands and generates block control pulses that temporarily suspend clock generation, removing the harmful continuous operation that causes phase flips while maintaining necessary clock functionality during normal operations
Solution Approach 2:
The patent implements feedback through the block control pulse generating circuit that monitors command addresses and detects self-refresh operations. This feedback mechanism triggers the block control signal to the clock division circuit, creating a closed-loop control system that automatically adjusts clock generation based on operational state, preventing phase flips during self-refresh while maintaining stability during normal operation
2Stability of the object's composition
If the clock division circuit stops generating division clocks during block section, then phase stability is maintained, but data input/output operations are interrupted
Solution Approach 1:
The patent applies periodic action by implementing block control pulses that temporarily suspend clock generation only during specific self-refresh intervals. This periodic blocking allows the system to maintain phase stability during critical operations while resuming normal high-speed data input/output operations during regular functioning, creating a rhythm of controlled interruption that balances stability and productivity
Data Source
AI summary
A semiconductor device includes a command decoder configured to generate a block command, based on a command address, and a clock division circuit configured to divide an internal clock and an inverted internal clock to generate division clocks. In the present disclosure, the clock division circuit is configured to stop generating the division clocks for a block section when the block command is generated.