Division Square Root Arithmetic Unit Radix Optimization

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Solution Overview

Problem

Existing division and square root arithmetic units face performance deterioration when attempting to perform higher radix division and square root extraction operations due to the complexity and increased logic stages required for square root extraction, which complicates circuitry and prolongs processing time.

Innovation Solution

A division and square root arithmetic unit is designed to share components between division and square root extraction, utilizing a higher radix for division and a lower radix for square root extraction, incorporating a quotient producer, partial remainder registers, a divisor-partial square root selector, carry save and propagation adders, and twos complement conversion and shift devices to optimize performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a higher radix is used for division operation, then division processing speed is improved, but square root extraction circuit complexity increases and processing time is prolonged

Engineering Contradiction:
Improvedivision processing speedVSAvoidsquare root extraction circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies different radix values to different operational modes: radix-4 for division operations and radix-2 for square root extraction operations. This local differentiation allows the circuit to optimize for division speed while maintaining manageable complexity for square root extraction, resolving the contradiction between division performance and overall circuit complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The circuit dynamically switches between radix-4 and radix-2 operational modes based on the type of operation being performed (division or square root extraction). This dynamic adaptability enables the system to achieve high division processing speed when needed while preventing excessive circuit complexity from affecting square root extraction performance

Inventive Principle:
Principle #15Dynamics

2Productivity

If a higher radix is used for division operation, then processing efficiency is improved, but logic stages increase and circuitry is complicated

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidcircuitry complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements radix-4 logic specifically for division operations where higher processing efficiency is beneficial, while using radix-2 logic for square root extraction where circuit simplicity is more important. This localized application of different radix values optimizes processing efficiency for division without unnecessarily complicating the overall circuitry

Inventive Principle:
Principle #3Local quality

3Productivity

If square root extraction is performed with higher radix, then extraction speed is improved, but circuit complexity and logic stages increase significantly

Engineering Contradiction:
Improveextraction speedVSAvoidlogic stages
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies radix-2 for square root extraction operations, maintaining circuit simplicity and manageable logic stages. By not forcing higher radix on square root extraction, the patent avoids significant increases in circuit complexity while still achieving functional performance through the optimized division capability

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7921149B2Division and square root arithmetic unit
Publication Date: 2011.04.05 NEC CORP
  • US7921149B2 patent drawing
  • US7921149B2 patent drawing
  • US7921149B2 patent drawing

AI summary

A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of a carry save adder and the output of the adder are input to convert the data into twos complement representation data, and the twos complement representation data is shifted a certain bit number (determined on the basis of the radix of the operation) to use the shifted data for a partial remainder of the next digit. Hence, a large number of parts such as registers of a divisor and a partially extracted square root can be commonly used in a divider and a square root extractor to realize an effective and high performance arithmetic unit.