Divoted Semiconductor Fin Isolation for Radiation-Hardened SRAM
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Solution Overview
Problem
FINFETs in memory cells are more susceptible to radiation-induced single event upsets (SEUs) due to lower device-to-substrate geometric isolation, resulting in a higher soft error rate (SER).
Innovation Solution
The semiconductor structure incorporates semiconductor fins with divots in the opposing sidewalls at the base, enhancing geometric isolation from the substrate. The fins extend above an isolation region on the substrate, improving radiation hardness and reducing SER.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FINFETs are used in memory cells to improve performance, then device performance is improved, but susceptibility to radiation-induced SEUs increases
Solution Approach 1:
The semiconductor fin is segmented by introducing divots that create distinct regions: a lower portion with divots for isolation and an upper portion for active device operation. This segmentation allows the lower portion to provide geometric isolation from the substrate while the upper portion maintains the necessary structure for high-performance FINFET operation, thereby resolving the contradiction between performance and radiation hardness.
Solution Approach 2:
The divots are localized to specific regions of the fin structure - specifically in the lower portion of the opposing sidewalls - rather than uniformly throughout. This local modification provides enhanced geometric isolation precisely where it is needed to reduce radiation-induced SEUs, while preserving the fin's overall structure and electrical performance characteristics in the upper portion.
2Reliability
If geometric isolation is increased to reduce SER, then radiation hardness is improved, but device structure complexity increases
Solution Approach 1:
The fin structure is divided into functional segments with divots created in the lower portion. This segmentation achieves improved geometric isolation for radiation hardness without requiring complete restructuring of the entire fin, thus limiting the increase in complexity to only the necessary regions while maintaining simplicity elsewhere.
Solution Approach 2:
The isolation enhancement is applied locally through divots in specific regions rather than uniformly across the entire fin structure. This localized approach improves radiation hardness where most needed at the fin-substrate interface while avoiding unnecessary complexity in the upper active regions of the fin.
Data Source
AI summary
Disclosed semiconductor structures include semiconductor fin(s), each extending from a semiconductor substrate and having opposing sidewalls. Each fin has a lower portion and an upper portion above the lower portion. The lower portion has a base proximal to the semiconductor substrate and divots within the opposing sidewalls at the base. An isolation region is on the semiconductor substrate adjacent to the opposing sidewalls of each fin (e.g., including within the divots). The upper portion of each fin extends above the level of the top surface of the isolation region and can be incorporated into a single-fin or multi-fin fin-type device (e.g., a fin-type field effect transistor (FINFET)). In some embodiments, multiple single-fin and/or multi-fin FINFETs incorporating the upper portions of such fins can be incorporated into a memory cell, such as a static random access memory (SRAM) cell. Also disclosed herein are associated method embodiments.